Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:13.2 (ISE) - O.61xd Target Family: Spartan6
OS Platform: NT Target Device: xc6slx45
Project ID (random number) 7ee2193a1e174d3e9b15c4e297bbd323.1AD5A7EA410A4ED8AECFA1AFA25DB8A3.2 Target Package: csg484
Registration ID __123456789_123456_123456789 Target Speed: -3
Date Generated 2012-08-06T14:02:30 Tool Flow ISE
 
User Environment
OS Name Microsoft Windows XP Professional OS Release Service Pack 3 (build 2600)
CPU Name Intel(R) Core(TM)2 Duo CPU T5750 @ 2.00GHz CPU Speed 1995 MHz
OS Name Microsoft Windows XP Professional OS Release Service Pack 3 (build 2600)
CPU Name Intel(R) Core(TM)2 Duo CPU T5750 @ 2.00GHz CPU Speed 1995 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Counters=1
  • 26-bit up counter=1
Multiplexers=1
  • 1-bit 8-to-1 multiplexer=1
Registers=9
  • Flip-Flops=9
MiscellaneousStatistics
  • AGG_BONDED_IO=13
  • AGG_IO=13
  • AGG_LOCED_IO=13
  • AGG_SLICE=9
  • NUM_BONDED_IOB=13
  • NUM_BSFULL=31
  • NUM_BSLUTONLY=2
  • NUM_BSUSED=33
  • NUM_BUFG=1
  • NUM_LOCED_IOB=13
  • NUM_LOGIC_O5ANDO6=1
  • NUM_LOGIC_O5ONLY=24
  • NUM_LOGIC_O6ONLY=4
  • NUM_LUT_RT_DRIVES_CARRY4=1
  • NUM_LUT_RT_DRIVES_FLOP=3
  • NUM_LUT_RT_EXO5=3
  • NUM_LUT_RT_EXO6=1
  • NUM_LUT_RT_O5=1
  • NUM_LUT_RT_O6=24
  • NUM_SLICEL=8
  • NUM_SLICEX=1
  • NUM_SLICE_CARRY4=7
  • NUM_SLICE_CONTROLSET=3
  • NUM_SLICE_CYINIT=60
  • NUM_SLICE_F7MUX=1
  • NUM_SLICE_FF=35
  • NUM_UNUSABLE_FF_BELS=13
NetStatistics
  • NumNets_Active=61
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BOUNCEACROSS=1
  • NumNodesOfType_Active_BOUNCEIN=9
  • NumNodesOfType_Active_BUFGOUT=1
  • NumNodesOfType_Active_BUFHINP2OUT=1
  • NumNodesOfType_Active_CLKPIN=9
  • NumNodesOfType_Active_CLKPINFEED=1
  • NumNodesOfType_Active_CNTRLPIN=9
  • NumNodesOfType_Active_DOUBLE=19
  • NumNodesOfType_Active_GENERIC=17
  • NumNodesOfType_Active_GLOBAL=11
  • NumNodesOfType_Active_INPUT=7
  • NumNodesOfType_Active_IOBIN2OUT=12
  • NumNodesOfType_Active_IOBOUTPUT=12
  • NumNodesOfType_Active_LUTINPUT=44
  • NumNodesOfType_Active_OUTBOUND=44
  • NumNodesOfType_Active_OUTPUT=44
  • NumNodesOfType_Active_PADINPUT=8
  • NumNodesOfType_Active_PADOUTPUT=5
  • NumNodesOfType_Active_PINBOUNCE=21
  • NumNodesOfType_Active_PINFEED=70
  • NumNodesOfType_Active_QUAD=33
  • NumNodesOfType_Active_REGINPUT=4
  • NumNodesOfType_Active_SINGLE=33
SiteStatistics
  • BUFG-BUFGMUX=1
  • IOB-IOBM=6
  • IOB-IOBS=7
  • SLICEL-SLICEM=7
SiteSummary
  • BUFG=1
  • BUFG_BUFG=1
  • CARRY4=7
  • FF_SR=4
  • HARD0=1
  • IOB=13
  • IOB_IMUX=5
  • IOB_INBUF=5
  • IOB_OUTBUF=8
  • LUT5=29
  • LUT6=30
  • PAD=13
  • REG_SR=31
  • SELMUX2_1=1
  • SLICEL=8
  • SLICEX=1
 
Configuration Data
FF_SR
  • CK=[CK:4] [CK_INV:0]
  • SRINIT=[SRINIT0:4]
  • SYNC_ATTR=[ASYNC:4]
IOB_OUTBUF
  • DRIVEATTRBOX=[12:8]
  • SLEW=[SLOW:8]
  • SUSPEND=[3STATE:8]
REG_SR
  • CK=[CK:31] [CK_INV:0]
  • LATCH_OR_FF=[FF:31]
  • SRINIT=[SRINIT0:31]
  • SYNC_ATTR=[ASYNC:31]
SLICEL
  • CLK=[CLK:8] [CLK_INV:0]
SLICEX
  • CLK=[CLK:1] [CLK_INV:0]
 
Pin Data
BUFG
  • I0=1
  • O=1
BUFG_BUFG
  • I0=1
  • O=1
CARRY4
  • CIN=6
  • CO3=6
  • CYINIT=1
  • DI0=7
  • DI1=6
  • DI2=6
  • DI3=6
  • O0=7
  • O1=7
  • O2=6
  • O3=6
  • S0=7
  • S1=7
  • S2=6
  • S3=6
FF_SR
  • CK=4
  • D=4
  • Q=4
  • SR=4
HARD0
  • 0=1
IOB
  • I=5
  • O=8
  • PAD=13
IOB_IMUX
  • I=5
  • OUT=5
IOB_INBUF
  • OUT=5
  • PAD=5
IOB_OUTBUF
  • IN=8
  • OUT=8
LUT5
  • A4=1
  • A5=3
  • O5=29
LUT6
  • A1=2
  • A2=2
  • A3=2
  • A4=28
  • A5=3
  • A6=29
  • O6=30
PAD
  • PAD=13
REG_SR
  • CE=1
  • CK=31
  • D=31
  • Q=31
  • SR=30
SELMUX2_1
  • 0=1
  • 1=1
  • OUT=1
  • S0=1
SLICEL
  • A=1
  • A4=7
  • A6=8
  • AQ=7
  • B4=7
  • B6=6
  • BQ=7
  • C1=1
  • C2=1
  • C3=1
  • C4=7
  • C5=1
  • C6=7
  • CE=1
  • CIN=6
  • CLK=8
  • COUT=6
  • CQ=7
  • CX=1
  • D1=1
  • D2=1
  • D3=1
  • D4=7
  • D5=1
  • D6=7
  • DQ=6
  • SR=7
SLICEX
  • A4=1
  • A5=1
  • A6=1
  • AMUX=1
  • AQ=1
  • B5=1
  • BMUX=1
  • BQ=1
  • BX=1
  • C5=1
  • CLK=1
  • CMUX=1
  • CQ=1
  • CX=1
  • D5=1
  • DMUX=1
  • DQ=1
  • DX=1
  • SR=1
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc6slx45-csg484-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx45-csg484-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg484-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx45-csg484-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 9 9 0 0 0 0 0
bitgen 44 44 0 0 0 0 0
bitinit 14 14 0 0 0 0 0
cse_server 24 24 0 0 0 0 0
elfcheck 7 7 0 0 0 0 0
libgen 3 3 0 0 0 0 0
map 49 48 0 0 0 0 0
ngc2edif 2 2 0 0 0 0 0
ngcbuild 155 155 0 0 0 0 0
ngdbuild 52 51 0 0 0 0 0
par 48 47 0 0 0 0 0
platgen 50 33 0 0 0 0 0
psf2Edward 3 3 0 0 0 0 0
trce 47 47 0 0 0 0 0
xps 31 31 0 0 0 0 0
xst 329 327 0 0 0 0 0
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2012-08-06T13:53:41
PROP_intWbtProjectID=1AD5A7EA410A4ED8AECFA1AFA25DB8A3 PROP_intWbtProjectIteration=2
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_lockPinsUcfFile=changed PROP_AutoTop=true
PROP_DevFamily=Spartan6 PROP_DevDevice=xc6slx45
PROP_DevFamilyPMName=spartan6 PROP_DevPackage=csg484
PROP_Synthesis_Tool=XST (VHDL/Verilog) PROP_DevSpeed=-3
PROP_PreferredLanguage=VHDL FILE_UCF=1
FILE_VHDL=1
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FDC=34 NGDBUILD_NUM_FDE=1 NGDBUILD_NUM_GND=1
NGDBUILD_NUM_IBUF=4 NGDBUILD_NUM_INV=3 NGDBUILD_NUM_LUT1=25 NGDBUILD_NUM_LUT6=2
NGDBUILD_NUM_MUXCY=25 NGDBUILD_NUM_MUXF7=1 NGDBUILD_NUM_OBUF=8 NGDBUILD_NUM_VCC=1
NGDBUILD_NUM_XORCY=26
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_FDC=34 NGDBUILD_NUM_FDE=1 NGDBUILD_NUM_GND=1
NGDBUILD_NUM_IBUF=4 NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=3 NGDBUILD_NUM_LUT1=25
NGDBUILD_NUM_LUT6=2 NGDBUILD_NUM_MUXCY=25 NGDBUILD_NUM_MUXF7=1 NGDBUILD_NUM_OBUF=8
NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=26
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ifmt=mixed -ofn=<design_top> -ofmt=NGC
-p=xc6slx45-3-csg484 -top=<design_top> -opt_mode=Speed -opt_level=1
-power=NO -iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized
-rtlview=Yes -glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO
-cross_clock_analysis=NO -bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100
-dsp_utilization_ratio=100 -reduce_control_sets=Auto -fsm_extract=YES -fsm_encoding=Auto
-safe_implementation=No -fsm_style=LUT -ram_extract=Yes -ram_style=Auto
-rom_extract=Yes -shreg_extract=YES -rom_style=Auto -auto_bram_packing=NO
-resource_sharing=YES -async_to_sync=NO -use_dsp48=Auto -iobuf=YES
-max_fanout=100000 -bufg=16 -register_duplication=YES -register_balancing=No
-optimize_primitives=NO -use_clock_enable=Auto -use_sync_set=Auto -use_sync_reset=Auto
-iob=Auto -equivalent_register_removal=YES -slice_utilization_ratio_maxmargin=5