Printable Version
Overview
Resources Used
1   MicroBlaze
1   Processor Local Bus (PLB) 4.6
2   Local Memory Bus (LMB) 1.0
1   Block RAM (BRAM) Block
2   LMB BRAM Controller
1   Multi-Port Memory Controller(DDR/DDR2/SDRAM)
1   XPS UART (Lite)
2   XPS General Purpose IO
1   XPS LocalLink Tri-mode Ethernet MAC
1   XPS Timer/Counter
1   XPS LocalLink FIFO
1   Clock Generator
1   MicroBlaze Debug Module (MDM)
1   Processor System Reset Module
1   XPS Interrupt Controller
1   Ethernet PHY MII to Reduced MII
Specifics
Generated Tue Jan 22 10:31:40 2013
EDK Version 13.4
Device Family spartan6
Device xc6slx45csg484-3

Block Diagram TOP

BlockDiagram
External Ports TOP

These are the external ports defined in the MHS file.
Attributes Key
The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file
CLK  indicates Clock ports, (SIGIS = CLK) 
INTR  indicates Interrupt ports,(SIGIS = INTR) 
RESET  indicates Reset ports, (SIGIS = RST) 
BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG) 
# NAME DIR [LSB:MSB] SIG ATTRIBUTES
SHARED fpga_0_rst_1_sys_rst_pin I 1 sys_rst_s  RESET 
DIP_Switches_8Bits fpga_0_DIP_Switches_8Bits_GPIO_IO_I_pin I 7:0 fpga_0_DIP_Switches_8Bits_GPIO_IO_I_pin
ETHERNET fpga_0_ETHERNET_MDIO_0_pin IO 1 fpga_0_ETHERNET_MDIO_0_pin
ETHERNET fpga_0_ETHERNET_MDC_0_pin O 1 fpga_0_ETHERNET_MDC_0_pin
LEDs_8Bits fpga_0_LEDs_8Bits_GPIO_IO_O_pin O 7:0 fpga_0_LEDs_8Bits_GPIO_IO_O_pin
MCB_DDR2 fpga_0_MCB_DDR2_mcbx_dram_dq_pin IO 0:15 fpga_0_MCB_DDR2_mcbx_dram_dq_pin
MCB_DDR2 fpga_0_MCB_DDR2_mcbx_dram_dqs_n_pin IO 1 fpga_0_MCB_DDR2_mcbx_dram_dqs_n_pin
MCB_DDR2 fpga_0_MCB_DDR2_mcbx_dram_dqs_pin IO 1 fpga_0_MCB_DDR2_mcbx_dram_dqs_pin
MCB_DDR2 fpga_0_MCB_DDR2_mcbx_dram_udqs_n_pin IO 1 fpga_0_MCB_DDR2_mcbx_dram_udqs_n_pin
MCB_DDR2 fpga_0_MCB_DDR2_mcbx_dram_udqs_pin IO 1 fpga_0_MCB_DDR2_mcbx_dram_udqs_pin
MCB_DDR2 fpga_0_MCB_DDR2_rzq_pin IO 1 fpga_0_MCB_DDR2_rzq_pin
MCB_DDR2 fpga_0_MCB_DDR2_zio_pin IO 1 fpga_0_MCB_DDR2_zio_pin
MCB_DDR2 fpga_0_MCB_DDR2_mcbx_dram_addr_pin O 0:12 fpga_0_MCB_DDR2_mcbx_dram_addr_pin
MCB_DDR2 fpga_0_MCB_DDR2_mcbx_dram_ba_pin O 0:2 fpga_0_MCB_DDR2_mcbx_dram_ba_pin
MCB_DDR2 fpga_0_MCB_DDR2_mcbx_dram_cas_n_pin O 1 fpga_0_MCB_DDR2_mcbx_dram_cas_n_pin
MCB_DDR2 fpga_0_MCB_DDR2_mcbx_dram_cke_pin O 1 fpga_0_MCB_DDR2_mcbx_dram_cke_pin
MCB_DDR2 fpga_0_MCB_DDR2_mcbx_dram_clk_n_pin O 1 fpga_0_MCB_DDR2_mcbx_dram_clk_n_pin
MCB_DDR2 fpga_0_MCB_DDR2_mcbx_dram_clk_pin O 1 fpga_0_MCB_DDR2_mcbx_dram_clk_pin
MCB_DDR2 fpga_0_MCB_DDR2_mcbx_dram_ldm_pin O 1 fpga_0_MCB_DDR2_mcbx_dram_ldm_pin
MCB_DDR2 fpga_0_MCB_DDR2_mcbx_dram_odt_pin O 1 fpga_0_MCB_DDR2_mcbx_dram_odt_pin
MCB_DDR2 fpga_0_MCB_DDR2_mcbx_dram_ras_n_pin O 1 fpga_0_MCB_DDR2_mcbx_dram_ras_n_pin
MCB_DDR2 fpga_0_MCB_DDR2_mcbx_dram_udm_pin O 1 fpga_0_MCB_DDR2_mcbx_dram_udm_pin
MCB_DDR2 fpga_0_MCB_DDR2_mcbx_dram_we_n_pin O 1 fpga_0_MCB_DDR2_mcbx_dram_we_n_pin
RS232_Uart_1 fpga_0_RS232_Uart_1_RX_pin I 1 fpga_0_RS232_Uart_1_RX_pin
RS232_Uart_1 fpga_0_RS232_Uart_1_TX_pin O 1 fpga_0_RS232_Uart_1_TX_pin
clock_generator_0 fpga_0_clk_1_sys_clk_pin I 1 CLK_S  CLK 
mii_to_rmii_0 mii_to_rmii_0_Phy2Rmii_crs_dv_pin I 1 mii_to_rmii_0_Phy2Rmii_crs_dv
mii_to_rmii_0 mii_to_rmii_0_Phy2Rmii_rx_er_pin I 1 mii_to_rmii_0_Phy2Rmii_rx_er
mii_to_rmii_0 mii_to_rmii_0_Phy2Rmii_rxd_pin I 0:1 mii_to_rmii_0_Phy2Rmii_rxd
mii_to_rmii_0 rmii_ref_clk I 1 mii_to_rmii_0_Ref_Clk  CLK 
mii_to_rmii_0 mii_to_rmii_0_Rmii2Phy_tx_en_pin O 1 mii_to_rmii_0_Rmii2Phy_tx_en
mii_to_rmii_0 mii_to_rmii_0_Rmii2Phy_txd_pin O 0:1 mii_to_rmii_0_Rmii2Phy_txd


Processors TOP

microblaze_0   MicroBlaze
The MicroBlaze 32 bit soft processor

IP Specs
Core Version Documentation
microblaze 8.20.b IP


microblaze_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 MB_RESET I 1 mb_reset
1 INTERRUPT I 1 microblaze_0_Interrupt
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
DLMB MASTER LMB dlmb dlmb_cntlr
ILMB MASTER LMB ilmb ilmb_cntlr
DPLB MASTER PLBV46 mb_plb 9 Peripherals.
IPLB MASTER PLBV46 mb_plb 9 Peripherals.
DEBUG TARGET XIL_MBDEBUG3 microblaze_0_mdm_bus mdm_0


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_SCO 0
C_FREQ 0
C_DATA_SIZE 32
C_DYNAMIC_BUS_SIZING 1
C_FAMILY virtex5
C_INSTANCE microblaze
C_AVOID_PRIMITIVES 0
C_FAULT_TOLERANT 0
C_ECC_USE_CE_EXCEPTION 0
C_LOCKSTEP_SLAVE 0
C_ENDIANNESS 0
C_AREA_OPTIMIZED 0
C_OPTIMIZATION 0
C_INTERCONNECT 1
C_STREAM_INTERCONNECT 0
C_DPLB_DWIDTH 32
C_DPLB_NATIVE_DWIDTH 32
C_DPLB_BURST_EN 0
C_DPLB_P2P 0
C_IPLB_DWIDTH 32
C_IPLB_NATIVE_DWIDTH 32
C_IPLB_BURST_EN 0
C_IPLB_P2P 0
C_M_AXI_DP_SUPPORTS_THREADS 0
C_M_AXI_DP_THREAD_ID_WIDTH 1
C_M_AXI_DP_SUPPORTS_READ 1
C_M_AXI_DP_SUPPORTS_WRITE 1
C_M_AXI_DP_SUPPORTS_NARROW_BURST 0
C_M_AXI_DP_DATA_WIDTH 32
C_M_AXI_DP_ADDR_WIDTH 32
C_M_AXI_DP_PROTOCOL AXI4LITE
C_M_AXI_DP_EXCLUSIVE_ACCESS 0
C_INTERCONNECT_M_AXI_DP_READ_ISSUING 1
C_INTERCONNECT_M_AXI_DP_WRITE_ISSUING 1
C_M_AXI_IP_SUPPORTS_THREADS 0
C_M_AXI_IP_THREAD_ID_WIDTH 1
C_M_AXI_IP_SUPPORTS_READ 1
C_M_AXI_IP_SUPPORTS_WRITE 0
C_M_AXI_IP_SUPPORTS_NARROW_BURST 0
C_M_AXI_IP_DATA_WIDTH 32
C_M_AXI_IP_ADDR_WIDTH 32
C_M_AXI_IP_PROTOCOL AXI4LITE
C_INTERCONNECT_M_AXI_IP_READ_ISSUING 1
C_D_AXI 0
C_D_PLB 0
C_D_LMB 1
C_I_AXI 0
C_I_PLB 0
C_I_LMB 1
C_USE_MSR_INSTR 1
C_USE_PCMP_INSTR 1
C_USE_BARREL 1
C_USE_DIV 0
C_USE_HW_MUL 1
C_USE_FPU 0
C_UNALIGNED_EXCEPTIONS 0
C_ILL_OPCODE_EXCEPTION 0
C_M_AXI_I_BUS_EXCEPTION 0
C_M_AXI_D_BUS_EXCEPTION 0
C_IPLB_BUS_EXCEPTION 0
C_DPLB_BUS_EXCEPTION 0
C_DIV_ZERO_EXCEPTION 0
C_FPU_EXCEPTION 0
C_FSL_EXCEPTION 0
C_USE_STACK_PROTECTION 0
C_PVR 0
C_PVR_USER1 0x00
C_PVR_USER2 0x00000000
C_DEBUG_ENABLED 1
C_NUMBER_OF_PC_BRK 1
C_NUMBER_OF_RD_ADDR_BRK 0
C_NUMBER_OF_WR_ADDR_BRK 0
C_INTERRUPT_IS_EDGE 0
C_EDGE_IS_POSITIVE 1
C_RESET_MSR 0x00000000
C_OPCODE_0x0_ILLEGAL 0
C_FSL_LINKS 0
C_FSL_DATA_SIZE 32
C_USE_EXTENDED_FSL_INSTR 0
C_M0_AXIS_PROTOCOL GENERIC
C_S0_AXIS_PROTOCOL GENERIC
C_M1_AXIS_PROTOCOL GENERIC
C_S1_AXIS_PROTOCOL GENERIC
C_M2_AXIS_PROTOCOL GENERIC
C_S2_AXIS_PROTOCOL GENERIC
C_M3_AXIS_PROTOCOL GENERIC
C_S3_AXIS_PROTOCOL GENERIC
C_M4_AXIS_PROTOCOL GENERIC
C_S4_AXIS_PROTOCOL GENERIC
C_M5_AXIS_PROTOCOL GENERIC
C_S5_AXIS_PROTOCOL GENERIC
C_M6_AXIS_PROTOCOL GENERIC
C_S6_AXIS_PROTOCOL GENERIC
C_M7_AXIS_PROTOCOL GENERIC
C_S7_AXIS_PROTOCOL GENERIC
C_M8_AXIS_PROTOCOL GENERIC
C_S8_AXIS_PROTOCOL GENERIC
C_M9_AXIS_PROTOCOL GENERIC
C_S9_AXIS_PROTOCOL GENERIC
C_M10_AXIS_PROTOCOL GENERIC
C_S10_AXIS_PROTOCOL GENERIC
C_M11_AXIS_PROTOCOL GENERIC
C_S11_AXIS_PROTOCOL GENERIC
C_M12_AXIS_PROTOCOL GENERIC
C_S12_AXIS_PROTOCOL GENERIC
C_M13_AXIS_PROTOCOL GENERIC
C_S13_AXIS_PROTOCOL GENERIC
C_M14_AXIS_PROTOCOL GENERIC
 
Name Value
C_S14_AXIS_PROTOCOL GENERIC
C_M15_AXIS_PROTOCOL GENERIC
C_S15_AXIS_PROTOCOL GENERIC
C_M0_AXIS_DATA_WIDTH 32
C_S0_AXIS_DATA_WIDTH 32
C_M1_AXIS_DATA_WIDTH 32
C_S1_AXIS_DATA_WIDTH 32
C_M2_AXIS_DATA_WIDTH 32
C_S2_AXIS_DATA_WIDTH 32
C_M3_AXIS_DATA_WIDTH 32
C_S3_AXIS_DATA_WIDTH 32
C_M4_AXIS_DATA_WIDTH 32
C_S4_AXIS_DATA_WIDTH 32
C_M5_AXIS_DATA_WIDTH 32
C_S5_AXIS_DATA_WIDTH 32
C_M6_AXIS_DATA_WIDTH 32
C_S6_AXIS_DATA_WIDTH 32
C_M7_AXIS_DATA_WIDTH 32
C_S7_AXIS_DATA_WIDTH 32
C_M8_AXIS_DATA_WIDTH 32
C_S8_AXIS_DATA_WIDTH 32
C_M9_AXIS_DATA_WIDTH 32
C_S9_AXIS_DATA_WIDTH 32
C_M10_AXIS_DATA_WIDTH 32
C_S10_AXIS_DATA_WIDTH 32
C_M11_AXIS_DATA_WIDTH 32
C_S11_AXIS_DATA_WIDTH 32
C_M12_AXIS_DATA_WIDTH 32
C_S12_AXIS_DATA_WIDTH 32
C_M13_AXIS_DATA_WIDTH 32
C_S13_AXIS_DATA_WIDTH 32
C_M14_AXIS_DATA_WIDTH 32
C_S14_AXIS_DATA_WIDTH 32
C_M15_AXIS_DATA_WIDTH 32
C_S15_AXIS_DATA_WIDTH 32
C_ICACHE_BASEADDR 0x00000000
C_ICACHE_HIGHADDR 0x3FFFFFFF
C_USE_ICACHE 0
C_ALLOW_ICACHE_WR 1
C_ADDR_TAG_BITS 17
C_CACHE_BYTE_SIZE 8192
C_ICACHE_USE_FSL 1
C_ICACHE_LINE_LEN 4
C_ICACHE_ALWAYS_USED 0
C_ICACHE_INTERFACE 0
C_ICACHE_VICTIMS 0
C_ICACHE_STREAMS 0
C_ICACHE_FORCE_TAG_LUTRAM 0
C_ICACHE_DATA_WIDTH 0
C_M_AXI_IC_SUPPORTS_THREADS 0
C_M_AXI_IC_THREAD_ID_WIDTH 1
C_M_AXI_IC_SUPPORTS_READ 1
C_M_AXI_IC_SUPPORTS_WRITE 0
C_M_AXI_IC_SUPPORTS_NARROW_BURST 0
C_M_AXI_IC_DATA_WIDTH 32
C_M_AXI_IC_ADDR_WIDTH 32
C_M_AXI_IC_PROTOCOL AXI4
C_M_AXI_IC_USER_VALUE 0b11111
C_M_AXI_IC_SUPPORTS_USER_SIGNALS 1
C_M_AXI_IC_AWUSER_WIDTH 5
C_M_AXI_IC_ARUSER_WIDTH 5
C_M_AXI_IC_WUSER_WIDTH 1
C_M_AXI_IC_RUSER_WIDTH 1
C_M_AXI_IC_BUSER_WIDTH 1
C_INTERCONNECT_M_AXI_IC_READ_ISSUING 2
C_DCACHE_BASEADDR 0x00000000
C_DCACHE_HIGHADDR 0x3FFFFFFF
C_USE_DCACHE 0
C_ALLOW_DCACHE_WR 1
C_DCACHE_ADDR_TAG 17
C_DCACHE_BYTE_SIZE 8192
C_DCACHE_USE_FSL 1
C_DCACHE_LINE_LEN 4
C_DCACHE_ALWAYS_USED 0
C_DCACHE_INTERFACE 0
C_DCACHE_USE_WRITEBACK 0
C_DCACHE_VICTIMS 0
C_DCACHE_FORCE_TAG_LUTRAM 0
C_DCACHE_DATA_WIDTH 0
C_M_AXI_DC_SUPPORTS_THREADS 0
C_M_AXI_DC_THREAD_ID_WIDTH 1
C_M_AXI_DC_SUPPORTS_READ 1
C_M_AXI_DC_SUPPORTS_WRITE 1
C_M_AXI_DC_SUPPORTS_NARROW_BURST 0
C_M_AXI_DC_DATA_WIDTH 32
C_M_AXI_DC_ADDR_WIDTH 32
C_M_AXI_DC_PROTOCOL AXI4
C_M_AXI_DC_EXCLUSIVE_ACCESS 0
C_M_AXI_DC_USER_VALUE 0b11111
C_M_AXI_DC_SUPPORTS_USER_SIGNALS 1
C_M_AXI_DC_AWUSER_WIDTH 5
C_M_AXI_DC_ARUSER_WIDTH 5
C_M_AXI_DC_WUSER_WIDTH 1
C_M_AXI_DC_RUSER_WIDTH 1
C_M_AXI_DC_BUSER_WIDTH 1
C_INTERCONNECT_M_AXI_DC_READ_ISSUING 2
C_INTERCONNECT_M_AXI_DC_WRITE_ISSUING 32
C_USE_MMU 0
C_MMU_DTLB_SIZE 4
C_MMU_ITLB_SIZE 2
C_MMU_TLB_ACCESS 3
C_MMU_ZONES 16
C_MMU_PRIVILEGED_INSTR 0
C_USE_INTERRUPT 0
C_USE_EXT_BRK 0
C_USE_EXT_NM_BRK 0
C_USE_BRANCH_TARGET_CACHE 0
C_BRANCH_TARGET_CACHE_SIZE 0
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




Debuggers TOP

mdm_0   MicroBlaze Debug Module (MDM)
Debug module for MicroBlaze Soft Processor.

IP Specs
Core Version Documentation
mdm 2.00.b IP


mdm_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 Debug_SYS_Rst O 1 Debug_SYS_Rst
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
MBDEBUG_0 INITIATOR XIL_MBDEBUG3 microblaze_0_mdm_bus microblaze_0
SPLB SLAVE PLBV46 mb_plb 9 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_JTAG_CHAIN 2
C_INTERCONNECT 1
C_BASEADDR 0x84400000
C_HIGHADDR 0x8440FFFF
C_SPLB_AWIDTH 32
C_SPLB_DWIDTH 32
C_SPLB_P2P 0
C_SPLB_MID_WIDTH 3
 
Name Value
C_SPLB_NUM_MASTERS 8
C_SPLB_NATIVE_DWIDTH 32
C_SPLB_SUPPORT_BURSTS 0
C_MB_DBG_PORTS 1
C_USE_UART 1
C_S_AXI_ADDR_WIDTH 32
C_S_AXI_DATA_WIDTH 32
C_S_AXI_PROTOCOL AXI4LITE
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




Interrupt Controllers TOP

xps_intc_0   XPS Interrupt Controller
intc core attached to the PLBV46

IP Specs
Core Version Documentation
xps_intc 2.01.a IP


xps_intc_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 Intr I 1 ETHERNET_TemacIntc0_Irpt & xps_timer_0_Interrupt & ETHERNET_fifo_IP2INTC_Irpt
1 Irq O 1 microblaze_0_Interrupt
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
SPLB SLAVE PLBV46 mb_plb 9 Peripherals.
Interrupt Priorities
Priority SIG MODULE
0 ETHERNET_TemacIntc0_Irpt ETHERNET
1 xps_timer_0_Interrupt xps_timer_0
2 ETHERNET_fifo_IP2INTC_Irpt ETHERNET_fifo


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex5
C_BASEADDR 0x81800000
C_HIGHADDR 0x8180FFFF
C_SPLB_AWIDTH 32
C_SPLB_DWIDTH 32
C_SPLB_P2P 0
C_SPLB_NUM_MASTERS 1
C_SPLB_MID_WIDTH 1
C_SPLB_NATIVE_DWIDTH 32
C_SPLB_SUPPORT_BURSTS 0
 
Name Value
C_NUM_INTR_INPUTS 2
C_KIND_OF_INTR 0xFFFFFFFF
C_KIND_OF_EDGE 0xFFFFFFFF
C_KIND_OF_LVL 0xFFFFFFFF
C_HAS_IPR 1
C_HAS_SIE 1
C_HAS_CIE 1
C_HAS_IVR 1
C_IRQ_IS_LEVEL 1
C_IRQ_ACTIVE 1
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




Busses TOP

dlmb   Local Memory Bus (LMB) 1.0
'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'

IP Specs
Core Version Documentation
lmb_v10 2.00.b IP


dlmb IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 LMB_Clk I 1 clk_66_6667MHzPLL0
1 SYS_Rst I 1 sys_bus_reset
Bus Connections
INSTANCE INTERFACE TYPE INTERFACE NAME
microblaze_0 MASTER DLMB
dlmb_cntlr SLAVE SLMB


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_LMB_NUM_SLAVES 4
C_LMB_AWIDTH 32
C_LMB_DWIDTH 32
C_EXT_RESET_HIGH 1
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


ilmb   Local Memory Bus (LMB) 1.0
'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'

IP Specs
Core Version Documentation
lmb_v10 2.00.b IP


ilmb IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 LMB_Clk I 1 clk_66_6667MHzPLL0
1 SYS_Rst I 1 sys_bus_reset
Bus Connections
INSTANCE INTERFACE TYPE INTERFACE NAME
microblaze_0 MASTER ILMB
ilmb_cntlr SLAVE SLMB


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_LMB_NUM_SLAVES 4
C_LMB_AWIDTH 32
C_LMB_DWIDTH 32
C_EXT_RESET_HIGH 1
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


mb_plb   Processor Local Bus (PLB) 4.6
'Xilinx 64-bit Processor Local Bus (PLB) consists of a bus control unit, a watchdog timer, and separate address, write, and read data path units with a a three-cycle only arbitration feature'

IP Specs
Core Version Documentation
plb_v46 1.05.a IP


mb_plb IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 PLB_Clk I 1 clk_66_6667MHzPLL0
1 SYS_Rst I 1 sys_bus_reset
Bus Connections
INSTANCE INTERFACE TYPE INTERFACE NAME
microblaze_0 MASTER DPLB
microblaze_0 MASTER IPLB
RS232_Uart_1 SLAVE SPLB
DIP_Switches_8Bits SLAVE SPLB
LEDs_8Bits SLAVE SPLB
MCB_DDR2 SLAVE SPLB0
ETHERNET SLAVE SPLB
xps_timer_0 SLAVE SPLB
ETHERNET_fifo SLAVE SPLB
mdm_0 SLAVE SPLB
xps_intc_0 SLAVE SPLB


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_PLBV46_NUM_MASTERS 4
C_PLBV46_NUM_SLAVES 8
C_PLBV46_MID_WIDTH 2
C_PLBV46_AWIDTH 32
C_PLBV46_DWIDTH 64
C_DCR_INTFCE 0
C_BASEADDR 0B1111111111
C_HIGHADDR 0B0000000000
C_DCR_AWIDTH 10
 
Name Value
C_DCR_DWIDTH 32
C_EXT_RESET_HIGH 1
C_IRQ_ACTIVE 1
C_NUM_CLK_PLB2OPB_REARB 5
C_ADDR_PIPELINING_TYPE 1
C_FAMILY virtex5
C_P2P 0
C_ARB_TYPE 0
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




Memorys TOP

lmb_bram   Block RAM (BRAM) Block
The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.

IP Specs
Core Version Documentation
bram_block 1.00.a IP


lmb_bram IP Image
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
PORTA TARGET XIL_BRAM ilmb_port ilmb_cntlr
PORTB TARGET XIL_BRAM dlmb_port dlmb_cntlr


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_MEMSIZE 2048
C_PORT_DWIDTH 32
C_PORT_AWIDTH 32
C_NUM_WE 4
C_FAMILY virtex2
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




Memory Controllers TOP

MCB_DDR2   Multi-Port Memory Controller(DDR/DDR2/SDRAM)
Multi-port memory controller.

IP Specs
Core Version Documentation
mpmc 6.05.a IP


MCB_DDR2 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 MPMC_Clk0 I 1 clk_66_6667MHzPLL0
1 MPMC_Rst I 1 sys_periph_reset
2 MPMC_Clk_Mem_2x I 1 clk_600_0000MHzPLL0_nobuf
3 MPMC_Clk_Mem_2x_180 I 1 clk_600_0000MHz180PLL0_nobuf
4 MPMC_PLL_Lock I 1 Dcm_all_locked
5 mcbx_dram_addr O 1 fpga_0_MCB_DDR2_mcbx_dram_addr_pin
6 mcbx_dram_ba O 1 fpga_0_MCB_DDR2_mcbx_dram_ba_pin
7 mcbx_dram_ras_n O 1 fpga_0_MCB_DDR2_mcbx_dram_ras_n_pin
8 mcbx_dram_cas_n O 1 fpga_0_MCB_DDR2_mcbx_dram_cas_n_pin
9 mcbx_dram_we_n O 1 fpga_0_MCB_DDR2_mcbx_dram_we_n_pin
10 mcbx_dram_cke O 1 fpga_0_MCB_DDR2_mcbx_dram_cke_pin
11 mcbx_dram_clk O 1 fpga_0_MCB_DDR2_mcbx_dram_clk_pin
12 mcbx_dram_clk_n O 1 fpga_0_MCB_DDR2_mcbx_dram_clk_n_pin
13 mcbx_dram_dq IO 1 fpga_0_MCB_DDR2_mcbx_dram_dq_pin
14 mcbx_dram_dqs IO 1 fpga_0_MCB_DDR2_mcbx_dram_dqs_pin
15 mcbx_dram_dqs_n IO 1 fpga_0_MCB_DDR2_mcbx_dram_dqs_n_pin
16 mcbx_dram_udqs IO 1 fpga_0_MCB_DDR2_mcbx_dram_udqs_pin
17 mcbx_dram_udqs_n IO 1 fpga_0_MCB_DDR2_mcbx_dram_udqs_n_pin
18 mcbx_dram_udm O 1 fpga_0_MCB_DDR2_mcbx_dram_udm_pin
19 mcbx_dram_ldm O 1 fpga_0_MCB_DDR2_mcbx_dram_ldm_pin
20 mcbx_dram_odt O 1 fpga_0_MCB_DDR2_mcbx_dram_odt_pin
21 rzq IO 1 fpga_0_MCB_DDR2_rzq_pin
22 zio IO 1 fpga_0_MCB_DDR2_zio_pin
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
SPLB0 SLAVE PLBV46 mb_plb 9 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex5
C_BASEFAMILY virtex5
C_SUBFAMILY fx
C_DEVICE 5vlx50t
C_PACKAGE ff1136
C_SPEEDGRADE -1
C_SPEEDGRADE_INT 1
C_NUM_PORTS 1
C_PORT_CONFIG 1
C_ALL_PIMS_SHARE_ADDRESSES 1
C_MPMC_BASEADDR 0x88000000
C_MPMC_HIGHADDR 0x8FFFFFFF
C_MPMC_SW_BASEADDR 0xFFFFFFFF
C_MPMC_SW_HIGHADDR 0x00000000
C_SDMA_CTRL_BASEADDR 0xFFFFFFFF
C_SDMA_CTRL_HIGHADDR 0x00000000
C_MPMC_CTRL_BASEADDR 0xFFFFFFFF
C_MPMC_CTRL_HIGHADDR 0x00000000
C_MPMC_CTRL_AWIDTH 32
C_MPMC_CTRL_DWIDTH 64
C_MPMC_CTRL_NATIVE_DWIDTH 32
C_MPMC_CTRL_NUM_MASTERS 1
C_MPMC_CTRL_MID_WIDTH 1
C_MPMC_CTRL_P2P 1
C_MPMC_CTRL_SUPPORT_BURSTS 0
C_MPMC_CTRL_SMALLEST_MASTER 32
C_NUM_IDELAYCTRL 1
C_IDELAYCTRL_LOC NOT_SET
C_IODELAY_GRP NOT_SET
C_MCB_LOC MEMC3
C_MMCM_EXT_LOC NOT_SET
C_MMCM_INT_LOC NOT_SET
C_MAX_REQ_ALLOWED 1
C_ARB_PIPELINE 1
C_WR_DATAPATH_TML_PIPELINE 1
C_RD_DATAPATH_TML_MAX_FANOUT 0
C_ARB_USE_DEFAULT 0
C_ARB0_ALGO ROUND_ROBIN
C_ARB0_NUM_SLOTS 8
C_ARB0_SLOT0 01234567
C_ARB0_SLOT1 12345670
C_ARB0_SLOT2 23456701
C_ARB0_SLOT3 34567012
C_ARB0_SLOT4 45670123
C_ARB0_SLOT5 56701234
C_ARB0_SLOT6 67012345
C_ARB0_SLOT7 70123456
C_ARB0_SLOT8 01234567
C_ARB0_SLOT9 12345670
C_ARB0_SLOT10 23456701
C_ARB0_SLOT11 34567012
C_ARB0_SLOT12 45670123
C_ARB0_SLOT13 56701234
C_ARB0_SLOT14 67012345
C_ARB0_SLOT15 70123456
C_PM_ENABLE 0
C_PM_DC_WIDTH 48
C_PM_GC_CNTR 1
C_PM_GC_WIDTH 48
C_PM_SHIFT_CNT_BY 1
C_SKIP_SIM_INIT_DELAY 0
C_USE_MIG_S3_PHY 0
C_USE_MIG_V4_PHY 0
C_USE_MIG_V5_PHY 0
C_USE_MIG_V6_PHY 0
C_USE_MCB_S6_PHY 0
C_USE_STATIC_PHY 0
C_STATIC_PHY_RDDATA_CLK_SEL 0
C_STATIC_PHY_RDDATA_SWAP_RISE 0
C_STATIC_PHY_RDEN_DELAY 5
C_DEBUG_REG_ENABLE 0
C_SPECIAL_BOARD NONE
C_USE_MIG_FLOW 0
C_MEM_ADDR_ORDER BANK_ROW_COLUMN
C_MEM_CALIBRATION_MODE 1
C_MEM_CALIBRATION_DELAY HALF
C_MEM_CALIBRATION_SOFT_IP TRUE
C_MEM_CALIBRATION_BYPASS NO
C_MPMC_MCB_DRP_CLK_PRESENT 0
C_MEM_SKIP_IN_TERM_CAL 0
C_MEM_SKIP_DYNAMIC_CAL 0
C_MEM_SKIP_DYN_IN_TERM 1
C_MEM_INCDEC_THRESHOLD 0x02
C_MEM_CHECK_MAX_INDELAY 0
C_MEM_CHECK_MAX_TAP_REG 0
C_MEM_TZQINIT_MAXCNT 528
C_MPMC_CLK_MEM_2X_PERIOD_PS 1
C_MCB_USE_EXTERNAL_BUFPLL 0
C_MCB_LDQSP_TAP_DELAY_VAL 0
C_MCB_UDQSP_TAP_DELAY_VAL 0
C_MCB_LDQSN_TAP_DELAY_VAL 0
C_MCB_UDQSN_TAP_DELAY_VAL 0
C_MCB_DQ0_TAP_DELAY_VAL 0
C_MCB_DQ1_TAP_DELAY_VAL 0
C_MCB_DQ2_TAP_DELAY_VAL 0
C_MCB_DQ3_TAP_DELAY_VAL 0
C_MCB_DQ4_TAP_DELAY_VAL 0
C_MCB_DQ5_TAP_DELAY_VAL 0
C_MCB_DQ6_TAP_DELAY_VAL 0
C_MCB_DQ7_TAP_DELAY_VAL 0
C_MCB_DQ8_TAP_DELAY_VAL 0
C_MCB_DQ9_TAP_DELAY_VAL 0
C_MCB_DQ10_TAP_DELAY_VAL 0
C_MCB_DQ11_TAP_DELAY_VAL 0
C_MCB_DQ12_TAP_DELAY_VAL 0
C_MCB_DQ13_TAP_DELAY_VAL 0
C_MCB_DQ14_TAP_DELAY_VAL 0
C_MCB_DQ15_TAP_DELAY_VAL 0
C_MCB_RZQ_LOC AA2
C_MCB_ZIO_LOC Y2
C_MEM_TYPE DDR2
C_MEM_PARTNO EDE1116AXXX-8E
C_MEM_PART_DATA_DEPTH 16
C_MEM_PART_DATA_WIDTH 8
C_MEM_PART_NUM_BANK_BITS 2
C_MEM_PART_NUM_ROW_BITS 13
C_MEM_PART_NUM_COL_BITS 9
C_MEM_PART_TRAS 0
C_MEM_PART_TRASMAX 0
C_MEM_PART_TRC 0
C_MEM_PART_TRCD 0
C_MEM_PART_TDQSS 1
C_MEM_PART_TWR 0
C_MEM_PART_TRP 0
C_MEM_PART_TMRD 4
C_MEM_PART_TRRD 0
C_MEM_PART_TRFC 0
C_MEM_PART_TREFI 0
C_MEM_PART_TAL 0
C_MEM_PART_TCCD 0
C_MEM_PART_TWTR 0
C_MEM_PART_TRTP 7500
C_MEM_PART_TZQINIT 512
C_MEM_PART_TZQCS 64
C_MEM_PART_TPRDI 1000000
C_MEM_PART_TZQI 128000000
C_MEM_PART_CAS_A_FMAX 0
C_MEM_PART_CAS_A 0
C_MEM_PART_CAS_B_FMAX 0
C_MEM_PART_CAS_B 0
C_MEM_PART_CAS_C_FMAX 0
C_MEM_PART_CAS_C 0
C_MEM_PART_CAS_D_FMAX 0
C_MEM_PART_CAS_D 0
C_MPMC_CLK0_PERIOD_PS 1
C_MPMC_CLK_MEM_PERIOD_PS 1
C_MEM_CAS_LATENCY 3
C_MEM_ODT_TYPE 3
C_MEM_REDUCED_DRV 0
C_MEM_REG_DIMM 0
C_MEM_CLK_WIDTH 1
C_MEM_ODT_WIDTH 1
C_MEM_CE_WIDTH 1
C_MEM_CS_N_WIDTH 1
C_MEM_ADDR_WIDTH 13
C_MEM_BANKADDR_WIDTH 2
C_MEM_DATA_WIDTH 16
C_MEM_BITS_DATA_PER_DQS 8
C_MEM_DM_WIDTH 8
C_MEM_DQS_WIDTH 8
C_MEM_NUM_DIMMS 1
C_MEM_NUM_RANKS 1
C_MEM_DQS_IO_COL 0x000000000000000000
C_MEM_DQ_IO_MS 0x000000000000000000
C_DDR2_DQSN_ENABLE 1
C_INCLUDE_ECC_SUPPORT 0
C_ECC_DEFAULT_ON 1
C_INCLUDE_ECC_TEST 0
C_ECC_SEC_THRESHOLD 1
C_ECC_DEC_THRESHOLD 1
C_ECC_PEC_THRESHOLD 1
C_ECC_DATA_WIDTH 0
C_ECC_DM_WIDTH 0
C_ECC_DQS_WIDTH 0
C_MEM_PA_SR 0
C_MEM_CAS_WR_LATENCY 5
C_MEM_AUTO_SR ENABLED
C_MEM_HIGH_TEMP_SR NORMAL
C_MEM_DYNAMIC_WRITE_ODT OFF
C_MEM_WRLVL 1
C_IDELAY_CLK_FREQ DEFAULT
C_MEM_PHASE_DETECT DEFAULT
C_MEM_IBUF_LPWR_MODE DEFAULT
C_MEM_IODELAY_HP_MODE DEFAULT
C_MEM_SIM_INIT_OPTION DEFAULT
C_MEM_SIM_CAL_OPTION DEFAULT
C_MEM_CAL_WIDTH DEFAULT
C_MEM_NDQS_COL0 0
C_MEM_NDQS_COL1 0
C_MEM_NDQS_COL2 0
C_MEM_NDQS_COL3 0
C_MEM_DQS_LOC_COL0 0x000000000000000000000000000000000000
C_MEM_DQS_LOC_COL1 0x000000000000000000000000000000000000
C_MEM_DQS_LOC_COL2 0x000000000000000000000000000000000000
C_MEM_DQS_LOC_COL3 0x000000000000000000000000000000000000
C_MAINT_PRESCALER_PERIOD 200000
C_TBY4TAPVALUE 9999
C_PIM0_BASEADDR 0xFFFFFFFF
C_PIM0_HIGHADDR 0x00000000
C_PIM0_OFFSET 0x00000000
C_PIM0_DATA_WIDTH 64
C_PIM0_BASETYPE 2
C_PIM0_SUBTYPE PLB
C_XCL0_LINESIZE 4
C_XCL0_WRITEXFER 1
C_XCL0_PIPE_STAGES 2
C_XCL0_B_IN_USE 0
C_PIM0_B_SUBTYPE INACTIVE
C_XCL0_B_LINESIZE 4
C_XCL0_B_WRITEXFER 1
C_SPLB0_AWIDTH 32
C_SPLB0_DWIDTH 64
C_SPLB0_NATIVE_DWIDTH 64
C_SPLB0_NUM_MASTERS 1
C_SPLB0_MID_WIDTH 1
C_SPLB0_P2P 1
C_SPLB0_SUPPORT_BURSTS 0
C_SPLB0_SMALLEST_MASTER 32
C_SDMA_CTRL0_BASEADDR 0xFFFFFFFF
C_SDMA_CTRL0_HIGHADDR 0x00000000
C_SDMA_CTRL0_AWIDTH 32
C_SDMA_CTRL0_DWIDTH 64
C_SDMA_CTRL0_NATIVE_DWIDTH 32
C_SDMA_CTRL0_NUM_MASTERS 1
C_SDMA_CTRL0_MID_WIDTH 1
C_SDMA_CTRL0_P2P 1
C_SDMA_CTRL0_SUPPORT_BURSTS 0
C_SDMA_CTRL0_SMALLEST_MASTER 32
C_SDMA0_COMPLETED_ERR_TX 1
C_SDMA0_COMPLETED_ERR_RX 1
C_SDMA0_PRESCALAR 1023
C_SDMA0_PI2LL_CLK_RATIO 1
C_PPC440MC0_BURST_LENGTH 4
C_PPC440MC0_PIPE_STAGES 1
C_VFBC0_CMD_FIFO_DEPTH 32
C_VFBC0_CMD_AFULL_COUNT 3
C_VFBC0_RDWD_DATA_WIDTH 32
C_VFBC0_RDWD_FIFO_DEPTH 1024
C_VFBC0_RD_AEMPTY_WD_AFULL_COUNT 3
C_PI0_RD_FIFO_TYPE BRAM
C_PI0_WR_FIFO_TYPE BRAM
C_PI0_ADDRACK_PIPELINE 1
C_PI0_RD_FIFO_APP_PIPELINE 1
C_PI0_RD_FIFO_MEM_PIPELINE 1
C_PI0_WR_FIFO_APP_PIPELINE 1
C_PI0_WR_FIFO_MEM_PIPELINE 1
C_PI0_PM_USED 1
C_PI0_PM_DC_CNTR 1
C_PIM1_BASEADDR 0xFFFFFFFF
C_PIM1_HIGHADDR 0x00000000
C_PIM1_OFFSET 0x00000000
C_PIM1_DATA_WIDTH 64
C_PIM1_BASETYPE 0
C_PIM1_SUBTYPE INACTIVE
C_XCL1_LINESIZE 4
C_XCL1_WRITEXFER 1
C_XCL1_PIPE_STAGES 2
C_XCL1_B_IN_USE 0
C_PIM1_B_SUBTYPE INACTIVE
C_XCL1_B_LINESIZE 4
C_XCL1_B_WRITEXFER 1
C_SPLB1_AWIDTH 32
C_SPLB1_DWIDTH 64
C_SPLB1_NATIVE_DWIDTH 64
C_SPLB1_NUM_MASTERS 1
C_SPLB1_MID_WIDTH 1
C_SPLB1_P2P 1
C_SPLB1_SUPPORT_BURSTS 0
C_SPLB1_SMALLEST_MASTER 32
C_SDMA_CTRL1_BASEADDR 0xFFFFFFFF
C_SDMA_CTRL1_HIGHADDR 0x00000000
C_SDMA_CTRL1_AWIDTH 32
C_SDMA_CTRL1_DWIDTH 64
C_SDMA_CTRL1_NATIVE_DWIDTH 32
C_SDMA_CTRL1_NUM_MASTERS 1
C_SDMA_CTRL1_MID_WIDTH 1
C_SDMA_CTRL1_P2P 1
C_SDMA_CTRL1_SUPPORT_BURSTS 0
C_SDMA_CTRL1_SMALLEST_MASTER 32
C_SDMA1_COMPLETED_ERR_TX 1
C_SDMA1_COMPLETED_ERR_RX 1
C_SDMA1_PRESCALAR 1023
C_SDMA1_PI2LL_CLK_RATIO 1
C_PPC440MC1_BURST_LENGTH 4
C_PPC440MC1_PIPE_STAGES 1
C_VFBC1_CMD_FIFO_DEPTH 32
C_VFBC1_CMD_AFULL_COUNT 3
C_VFBC1_RDWD_DATA_WIDTH 32
C_VFBC1_RDWD_FIFO_DEPTH 1024
C_VFBC1_RD_AEMPTY_WD_AFULL_COUNT 3
C_PI1_RD_FIFO_TYPE BRAM
C_PI1_WR_FIFO_TYPE BRAM
C_PI1_ADDRACK_PIPELINE 1
C_PI1_RD_FIFO_APP_PIPELINE 1
C_PI1_RD_FIFO_MEM_PIPELINE 1
C_PI1_WR_FIFO_APP_PIPELINE 1
C_PI1_WR_FIFO_MEM_PIPELINE 1
C_PI1_PM_USED 1
C_PI1_PM_DC_CNTR 1
C_PIM2_BASEADDR 0xFFFFFFFF
C_PIM2_HIGHADDR 0x00000000
C_PIM2_OFFSET 0x00000000
C_PIM2_DATA_WIDTH 64
C_PIM2_BASETYPE 0
C_PIM2_SUBTYPE INACTIVE
C_XCL2_LINESIZE 4
C_XCL2_WRITEXFER 1
C_XCL2_PIPE_STAGES 2
C_XCL2_B_IN_USE 0
C_PIM2_B_SUBTYPE INACTIVE
C_XCL2_B_LINESIZE 4
C_XCL2_B_WRITEXFER 1
C_SPLB2_AWIDTH 32
C_SPLB2_DWIDTH 64
C_SPLB2_NATIVE_DWIDTH 64
C_SPLB2_NUM_MASTERS 1
C_SPLB2_MID_WIDTH 1
C_SPLB2_P2P 1
C_SPLB2_SUPPORT_BURSTS 0
C_SPLB2_SMALLEST_MASTER 32
C_SDMA_CTRL2_BASEADDR 0xFFFFFFFF
C_SDMA_CTRL2_HIGHADDR 0x00000000
C_SDMA_CTRL2_AWIDTH 32
C_SDMA_CTRL2_DWIDTH 64
C_SDMA_CTRL2_NATIVE_DWIDTH 32
C_SDMA_CTRL2_NUM_MASTERS 1
C_SDMA_CTRL2_MID_WIDTH 1
C_SDMA_CTRL2_P2P 1
C_SDMA_CTRL2_SUPPORT_BURSTS 0
C_SDMA_CTRL2_SMALLEST_MASTER 32
C_SDMA2_COMPLETED_ERR_TX 1
C_SDMA2_COMPLETED_ERR_RX 1
C_SDMA2_PRESCALAR 1023
C_SDMA2_PI2LL_CLK_RATIO 1
C_PPC440MC2_BURST_LENGTH 4
C_PPC440MC2_PIPE_STAGES 1
C_VFBC2_CMD_FIFO_DEPTH 32
C_VFBC2_CMD_AFULL_COUNT 3
C_VFBC2_RDWD_DATA_WIDTH 32
C_VFBC2_RDWD_FIFO_DEPTH 1024
C_VFBC2_RD_AEMPTY_WD_AFULL_COUNT 3
C_PI2_RD_FIFO_TYPE BRAM
C_PI2_WR_FIFO_TYPE BRAM
C_PI2_ADDRACK_PIPELINE 1
C_PI2_RD_FIFO_APP_PIPELINE 1
C_PI2_RD_FIFO_MEM_PIPELINE 1
C_PI2_WR_FIFO_APP_PIPELINE 1
C_PI2_WR_FIFO_MEM_PIPELINE 1
C_PI2_PM_USED 1
C_PI2_PM_DC_CNTR 1
C_PIM3_BASEADDR 0xFFFFFFFF
C_PIM3_HIGHADDR 0x00000000
C_PIM3_OFFSET 0x00000000
C_PIM3_DATA_WIDTH 64
C_PIM3_BASETYPE 0
C_PIM3_SUBTYPE INACTIVE
C_XCL3_LINESIZE 4
C_XCL3_WRITEXFER 1
C_XCL3_PIPE_STAGES 2
C_XCL3_B_IN_USE 0
C_PIM3_B_SUBTYPE INACTIVE
C_XCL3_B_LINESIZE 4
C_XCL3_B_WRITEXFER 1
C_SPLB3_AWIDTH 32
C_SPLB3_DWIDTH 64
C_SPLB3_NATIVE_DWIDTH 64
C_SPLB3_NUM_MASTERS 1
C_SPLB3_MID_WIDTH 1
C_SPLB3_P2P 1
C_SPLB3_SUPPORT_BURSTS 0
C_SPLB3_SMALLEST_MASTER 32
C_SDMA_CTRL3_BASEADDR 0xFFFFFFFF
C_SDMA_CTRL3_HIGHADDR 0x00000000
C_SDMA_CTRL3_AWIDTH 32
C_SDMA_CTRL3_DWIDTH 64
C_SDMA_CTRL3_NATIVE_DWIDTH 32
C_SDMA_CTRL3_NUM_MASTERS 1
C_SDMA_CTRL3_MID_WIDTH 1
C_SDMA_CTRL3_P2P 1
C_SDMA_CTRL3_SUPPORT_BURSTS 0
C_SDMA_CTRL3_SMALLEST_MASTER 32
C_SDMA3_COMPLETED_ERR_TX 1
C_SDMA3_COMPLETED_ERR_RX 1
C_SDMA3_PRESCALAR 1023
C_SDMA3_PI2LL_CLK_RATIO 1
C_PPC440MC3_BURST_LENGTH 4
C_PPC440MC3_PIPE_STAGES 1
C_VFBC3_CMD_FIFO_DEPTH 32
C_VFBC3_CMD_AFULL_COUNT 3
C_VFBC3_RDWD_DATA_WIDTH 32
C_VFBC3_RDWD_FIFO_DEPTH 1024
C_VFBC3_RD_AEMPTY_WD_AFULL_COUNT 3
C_PI3_RD_FIFO_TYPE BRAM
C_PI3_WR_FIFO_TYPE BRAM
C_PI3_ADDRACK_PIPELINE 1
C_PI3_RD_FIFO_APP_PIPELINE 1
C_PI3_RD_FIFO_MEM_PIPELINE 1
C_PI3_WR_FIFO_APP_PIPELINE 1
C_PI3_WR_FIFO_MEM_PIPELINE 1
C_PI3_PM_USED 1
C_PI3_PM_DC_CNTR 1
C_PIM4_BASEADDR 0xFFFFFFFF
C_PIM4_HIGHADDR 0x00000000
C_PIM4_OFFSET 0x00000000
 
Name Value
C_PIM4_DATA_WIDTH 64
C_PIM4_BASETYPE 0
C_PIM4_SUBTYPE INACTIVE
C_XCL4_LINESIZE 4
C_XCL4_WRITEXFER 1
C_XCL4_PIPE_STAGES 2
C_XCL4_B_IN_USE 0
C_PIM4_B_SUBTYPE INACTIVE
C_XCL4_B_LINESIZE 4
C_XCL4_B_WRITEXFER 1
C_SPLB4_AWIDTH 32
C_SPLB4_DWIDTH 64
C_SPLB4_NATIVE_DWIDTH 64
C_SPLB4_NUM_MASTERS 1
C_SPLB4_MID_WIDTH 1
C_SPLB4_P2P 1
C_SPLB4_SUPPORT_BURSTS 0
C_SPLB4_SMALLEST_MASTER 32
C_SDMA_CTRL4_BASEADDR 0xFFFFFFFF
C_SDMA_CTRL4_HIGHADDR 0x00000000
C_SDMA_CTRL4_AWIDTH 32
C_SDMA_CTRL4_DWIDTH 64
C_SDMA_CTRL4_NATIVE_DWIDTH 32
C_SDMA_CTRL4_NUM_MASTERS 1
C_SDMA_CTRL4_MID_WIDTH 1
C_SDMA_CTRL4_P2P 1
C_SDMA_CTRL4_SUPPORT_BURSTS 0
C_SDMA_CTRL4_SMALLEST_MASTER 32
C_SDMA4_COMPLETED_ERR_TX 1
C_SDMA4_COMPLETED_ERR_RX 1
C_SDMA4_PRESCALAR 1023
C_SDMA4_PI2LL_CLK_RATIO 1
C_PPC440MC4_BURST_LENGTH 4
C_PPC440MC4_PIPE_STAGES 1
C_VFBC4_CMD_FIFO_DEPTH 32
C_VFBC4_CMD_AFULL_COUNT 3
C_VFBC4_RDWD_DATA_WIDTH 32
C_VFBC4_RDWD_FIFO_DEPTH 1024
C_VFBC4_RD_AEMPTY_WD_AFULL_COUNT 3
C_PI4_RD_FIFO_TYPE BRAM
C_PI4_WR_FIFO_TYPE BRAM
C_PI4_ADDRACK_PIPELINE 1
C_PI4_RD_FIFO_APP_PIPELINE 1
C_PI4_RD_FIFO_MEM_PIPELINE 1
C_PI4_WR_FIFO_APP_PIPELINE 1
C_PI4_WR_FIFO_MEM_PIPELINE 1
C_PI4_PM_USED 1
C_PI4_PM_DC_CNTR 1
C_PIM5_BASEADDR 0xFFFFFFFF
C_PIM5_HIGHADDR 0x00000000
C_PIM5_OFFSET 0x00000000
C_PIM5_DATA_WIDTH 64
C_PIM5_BASETYPE 0
C_PIM5_SUBTYPE INACTIVE
C_XCL5_LINESIZE 4
C_XCL5_WRITEXFER 1
C_XCL5_PIPE_STAGES 2
C_XCL5_B_IN_USE 0
C_PIM5_B_SUBTYPE INACTIVE
C_XCL5_B_LINESIZE 4
C_XCL5_B_WRITEXFER 1
C_SPLB5_AWIDTH 32
C_SPLB5_DWIDTH 64
C_SPLB5_NATIVE_DWIDTH 64
C_SPLB5_NUM_MASTERS 1
C_SPLB5_MID_WIDTH 1
C_SPLB5_P2P 1
C_SPLB5_SUPPORT_BURSTS 0
C_SPLB5_SMALLEST_MASTER 32
C_SDMA_CTRL5_BASEADDR 0xFFFFFFFF
C_SDMA_CTRL5_HIGHADDR 0x00000000
C_SDMA_CTRL5_AWIDTH 32
C_SDMA_CTRL5_DWIDTH 64
C_SDMA_CTRL5_NATIVE_DWIDTH 32
C_SDMA_CTRL5_NUM_MASTERS 1
C_SDMA_CTRL5_MID_WIDTH 1
C_SDMA_CTRL5_P2P 1
C_SDMA_CTRL5_SUPPORT_BURSTS 0
C_SDMA_CTRL5_SMALLEST_MASTER 32
C_SDMA5_COMPLETED_ERR_TX 1
C_SDMA5_COMPLETED_ERR_RX 1
C_SDMA5_PRESCALAR 1023
C_SDMA5_PI2LL_CLK_RATIO 1
C_PPC440MC5_BURST_LENGTH 4
C_PPC440MC5_PIPE_STAGES 1
C_VFBC5_CMD_FIFO_DEPTH 32
C_VFBC5_CMD_AFULL_COUNT 3
C_VFBC5_RDWD_DATA_WIDTH 32
C_VFBC5_RDWD_FIFO_DEPTH 1024
C_VFBC5_RD_AEMPTY_WD_AFULL_COUNT 3
C_PI5_RD_FIFO_TYPE BRAM
C_PI5_WR_FIFO_TYPE BRAM
C_PI5_ADDRACK_PIPELINE 1
C_PI5_RD_FIFO_APP_PIPELINE 1
C_PI5_RD_FIFO_MEM_PIPELINE 1
C_PI5_WR_FIFO_APP_PIPELINE 1
C_PI5_WR_FIFO_MEM_PIPELINE 1
C_PI5_PM_USED 1
C_PI5_PM_DC_CNTR 1
C_PIM6_BASEADDR 0xFFFFFFFF
C_PIM6_HIGHADDR 0x00000000
C_PIM6_OFFSET 0x00000000
C_PIM6_DATA_WIDTH 64
C_PIM6_BASETYPE 0
C_PIM6_SUBTYPE INACTIVE
C_XCL6_LINESIZE 4
C_XCL6_WRITEXFER 1
C_XCL6_PIPE_STAGES 2
C_XCL6_B_IN_USE 0
C_PIM6_B_SUBTYPE INACTIVE
C_XCL6_B_LINESIZE 4
C_XCL6_B_WRITEXFER 1
C_SPLB6_AWIDTH 32
C_SPLB6_DWIDTH 64
C_SPLB6_NATIVE_DWIDTH 64
C_SPLB6_NUM_MASTERS 1
C_SPLB6_MID_WIDTH 1
C_SPLB6_P2P 1
C_SPLB6_SUPPORT_BURSTS 0
C_SPLB6_SMALLEST_MASTER 32
C_SDMA_CTRL6_BASEADDR 0xFFFFFFFF
C_SDMA_CTRL6_HIGHADDR 0x00000000
C_SDMA_CTRL6_AWIDTH 32
C_SDMA_CTRL6_DWIDTH 64
C_SDMA_CTRL6_NATIVE_DWIDTH 32
C_SDMA_CTRL6_NUM_MASTERS 1
C_SDMA_CTRL6_MID_WIDTH 1
C_SDMA_CTRL6_P2P 1
C_SDMA_CTRL6_SUPPORT_BURSTS 0
C_SDMA_CTRL6_SMALLEST_MASTER 32
C_SDMA6_COMPLETED_ERR_TX 1
C_SDMA6_COMPLETED_ERR_RX 1
C_SDMA6_PRESCALAR 1023
C_SDMA6_PI2LL_CLK_RATIO 1
C_PPC440MC6_BURST_LENGTH 4
C_PPC440MC6_PIPE_STAGES 1
C_VFBC6_CMD_FIFO_DEPTH 32
C_VFBC6_CMD_AFULL_COUNT 3
C_VFBC6_RDWD_DATA_WIDTH 32
C_VFBC6_RDWD_FIFO_DEPTH 1024
C_VFBC6_RD_AEMPTY_WD_AFULL_COUNT 3
C_PI6_RD_FIFO_TYPE BRAM
C_PI6_WR_FIFO_TYPE BRAM
C_PI6_ADDRACK_PIPELINE 1
C_PI6_RD_FIFO_APP_PIPELINE 1
C_PI6_RD_FIFO_MEM_PIPELINE 1
C_PI6_WR_FIFO_APP_PIPELINE 1
C_PI6_WR_FIFO_MEM_PIPELINE 1
C_PI6_PM_USED 1
C_PI6_PM_DC_CNTR 1
C_PIM7_BASEADDR 0xFFFFFFFF
C_PIM7_HIGHADDR 0x00000000
C_PIM7_OFFSET 0x00000000
C_PIM7_DATA_WIDTH 64
C_PIM7_BASETYPE 0
C_PIM7_SUBTYPE INACTIVE
C_XCL7_LINESIZE 4
C_XCL7_WRITEXFER 1
C_XCL7_PIPE_STAGES 2
C_XCL7_B_IN_USE 0
C_PIM7_B_SUBTYPE INACTIVE
C_XCL7_B_LINESIZE 4
C_XCL7_B_WRITEXFER 1
C_SPLB7_AWIDTH 32
C_SPLB7_DWIDTH 64
C_SPLB7_NATIVE_DWIDTH 64
C_SPLB7_NUM_MASTERS 1
C_SPLB7_MID_WIDTH 1
C_SPLB7_P2P 1
C_SPLB7_SUPPORT_BURSTS 0
C_SPLB7_SMALLEST_MASTER 32
C_SDMA_CTRL7_BASEADDR 0xFFFFFFFF
C_SDMA_CTRL7_HIGHADDR 0x00000000
C_SDMA_CTRL7_AWIDTH 32
C_SDMA_CTRL7_DWIDTH 64
C_SDMA_CTRL7_NATIVE_DWIDTH 32
C_SDMA_CTRL7_NUM_MASTERS 1
C_SDMA_CTRL7_MID_WIDTH 1
C_SDMA_CTRL7_P2P 1
C_SDMA_CTRL7_SUPPORT_BURSTS 0
C_SDMA_CTRL7_SMALLEST_MASTER 32
C_SDMA7_COMPLETED_ERR_TX 1
C_SDMA7_COMPLETED_ERR_RX 1
C_SDMA7_PRESCALAR 1023
C_SDMA7_PI2LL_CLK_RATIO 1
C_PPC440MC7_BURST_LENGTH 4
C_PPC440MC7_PIPE_STAGES 1
C_VFBC7_CMD_FIFO_DEPTH 32
C_VFBC7_CMD_AFULL_COUNT 3
C_VFBC7_RDWD_DATA_WIDTH 32
C_VFBC7_RDWD_FIFO_DEPTH 1024
C_VFBC7_RD_AEMPTY_WD_AFULL_COUNT 3
C_PI7_RD_FIFO_TYPE BRAM
C_PI7_WR_FIFO_TYPE BRAM
C_PI7_ADDRACK_PIPELINE 1
C_PI7_RD_FIFO_APP_PIPELINE 1
C_PI7_RD_FIFO_MEM_PIPELINE 1
C_PI7_WR_FIFO_APP_PIPELINE 1
C_PI7_WR_FIFO_MEM_PIPELINE 1
C_PI7_PM_USED 1
C_PI7_PM_DC_CNTR 1
C_WR_TRAINING_PORT 0
C_ARB_BRAM_INIT_00 0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111010001000011000000001111111111110010000110100000000011111111111100001101000100000000111111111111011010001000
C_ARB_BRAM_INIT_01 0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111
C_ARB_BRAM_INIT_02 0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111011010001000000000001111111111110110100010000000000011111111111101101000100000000000111111111111011010001000
C_ARB_BRAM_INIT_03 0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111
C_ARB_BRAM_INIT_04 0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111010001000011000000001111111111110010000110100000000011111111111100001101000100000000111111111111011010001000
C_ARB_BRAM_INIT_05 0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111
C_ARB_BRAM_INIT_06 0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111011010001000000000001111111111110110100010000000000011111111111101101000100000000000111111111111011010001000
C_ARB_BRAM_INIT_07 0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111
C_NCK_PER_CLK 1
C_TWR 0
C_CTRL_COMPLETE_INDEX 0
C_CTRL_IS_WRITE_INDEX 0
C_CTRL_PHYIF_RAS_N_INDEX 0
C_CTRL_PHYIF_CAS_N_INDEX 0
C_CTRL_PHYIF_WE_N_INDEX 0
C_CTRL_RMW_INDEX 0
C_CTRL_SKIP_0_INDEX 0
C_CTRL_PHYIF_DQS_O_INDEX 0
C_CTRL_SKIP_1_INDEX 0
C_CTRL_DP_RDFIFO_PUSH_INDEX 0
C_CTRL_SKIP_2_INDEX 0
C_CTRL_AP_COL_CNT_LOAD_INDEX 0
C_CTRL_AP_COL_CNT_ENABLE_INDEX 0
C_CTRL_AP_PRECHARGE_ADDR10_INDEX 0
C_CTRL_AP_ROW_COL_SEL_INDEX 0
C_CTRL_PHYIF_FORCE_DM_INDEX 0
C_CTRL_REPEAT4_INDEX 0
C_CTRL_DFI_RAS_N_0_INDEX 0
C_CTRL_DFI_CAS_N_0_INDEX 0
C_CTRL_DFI_WE_N_0_INDEX 0
C_CTRL_DFI_RAS_N_1_INDEX 0
C_CTRL_DFI_CAS_N_1_INDEX 0
C_CTRL_DFI_WE_N_1_INDEX 0
C_CTRL_DP_WRFIFO_POP_INDEX 0
C_CTRL_DFI_WRDATA_EN_INDEX 0
C_CTRL_DFI_RDDATA_EN_INDEX 0
C_CTRL_AP_OTF_ADDR12_INDEX 0
C_CTRL_ARB_RDMODWR_DELAY 0
C_CTRL_AP_COL_DELAY 0
C_CTRL_AP_PI_ADDR_CE_DELAY 0
C_CTRL_AP_PORT_SELECT_DELAY 0
C_CTRL_AP_PIPELINE1_CE_DELAY 0
C_CTRL_DP_LOAD_RDWDADDR_DELAY 0
C_CTRL_DP_RDFIFO_WHICHPORT_DELAY 0
C_CTRL_DP_SIZE_DELAY 0
C_CTRL_DP_WRFIFO_WHICHPORT_DELAY 0
C_CTRL_PHYIF_DUMMYREADSTART_DELAY 0
C_CTRL_Q0_DELAY 0
C_CTRL_Q1_DELAY 0
C_CTRL_Q2_DELAY 0
C_CTRL_Q3_DELAY 0
C_CTRL_Q4_DELAY 0
C_CTRL_Q5_DELAY 0
C_CTRL_Q6_DELAY 0
C_CTRL_Q7_DELAY 0
C_CTRL_Q8_DELAY 0
C_CTRL_Q9_DELAY 0
C_CTRL_Q10_DELAY 0
C_CTRL_Q11_DELAY 0
C_CTRL_Q12_DELAY 0
C_CTRL_Q13_DELAY 0
C_CTRL_Q14_DELAY 0
C_CTRL_Q15_DELAY 0
C_CTRL_Q16_DELAY 0
C_CTRL_Q17_DELAY 0
C_CTRL_Q18_DELAY 0
C_CTRL_Q19_DELAY 0
C_CTRL_Q20_DELAY 0
C_CTRL_Q21_DELAY 0
C_CTRL_Q22_DELAY 0
C_CTRL_Q23_DELAY 0
C_CTRL_Q24_DELAY 0
C_CTRL_Q25_DELAY 0
C_CTRL_Q26_DELAY 0
C_CTRL_Q27_DELAY 0
C_CTRL_Q28_DELAY 0
C_CTRL_Q29_DELAY 0
C_CTRL_Q30_DELAY 0
C_CTRL_Q31_DELAY 0
C_CTRL_Q32_DELAY 0
C_CTRL_Q33_DELAY 0
C_CTRL_Q34_DELAY 0
C_CTRL_Q35_DELAY 0
C_SKIP_1_VALUE 15
C_SKIP_2_VALUE 15
C_SKIP_3_VALUE 15
C_SKIP_4_VALUE 20
C_SKIP_5_VALUE 36
C_SKIP_6_VALUE 20
C_SKIP_7_VALUE 36
C_B16_REPEAT_CNT 0
C_B32_REPEAT_CNT 0
C_B64_REPEAT_CNT 0
C_ZQCS_REPEAT_CNT 0
C_BASEADDR_CTRL0 0x000
C_HIGHADDR_CTRL0 0x00D
C_BASEADDR_CTRL1 0x00E
C_HIGHADDR_CTRL1 0x017
C_BASEADDR_CTRL2 0x018
C_HIGHADDR_CTRL2 0x025
C_BASEADDR_CTRL3 0x026
C_HIGHADDR_CTRL3 0x02F
C_BASEADDR_CTRL4 0x030
C_HIGHADDR_CTRL4 0x03D
C_BASEADDR_CTRL5 0x03E
C_HIGHADDR_CTRL5 0x047
C_BASEADDR_CTRL6 0x048
C_HIGHADDR_CTRL6 0x05B
C_BASEADDR_CTRL7 0x05C
C_HIGHADDR_CTRL7 0x06A
C_BASEADDR_CTRL8 0x06B
C_HIGHADDR_CTRL8 0x086
C_BASEADDR_CTRL9 0x087
C_HIGHADDR_CTRL9 0x09D
C_BASEADDR_CTRL10 0x09E
C_HIGHADDR_CTRL10 0x0A5
C_BASEADDR_CTRL11 0x0A6
C_HIGHADDR_CTRL11 0x0AD
C_BASEADDR_CTRL12 0x0AE
C_HIGHADDR_CTRL12 0x0B5
C_BASEADDR_CTRL13 0x0B6
C_HIGHADDR_CTRL13 0x0BD
C_BASEADDR_CTRL14 0x0BE
C_HIGHADDR_CTRL14 0x0D0
C_BASEADDR_CTRL15 0x0D1
C_HIGHADDR_CTRL15 0x0D8
C_BASEADDR_CTRL16 0x0D9
C_HIGHADDR_CTRL16 0x0DA
C_CTRL_BRAM_INIT_3F 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_3E 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_3D 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_3C 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_3B 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_3A 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_39 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_38 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_37 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_36 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_35 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_34 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_33 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_32 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_31 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_30 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_2F 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_2E 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_2D 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_2C 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_2B 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_2A 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_29 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_28 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_27 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_26 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_25 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_24 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_23 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_22 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_21 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_20 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_1F 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_1E 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_1D 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_1C 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_1B 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_1A 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_19 0x000002FC000002FC000002FC000002FC000002FD000002FC000002FC000002FC
C_CTRL_BRAM_INIT_18 0x000002FC000002FC000002FC000002FC000002FC000002F0000002FC000002FC
C_CTRL_BRAM_INIT_17 0x000002FC000042E8000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_16 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_15 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_14 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_13 0x000002FC000002FC000002FC000002FC000002FC000042E8000006FC000026F5
C_CTRL_BRAM_INIT_12 0x000006FC000026F4000006FC000026F4000006FC000026F4000006FC000026F4
C_CTRL_BRAM_INIT_11 0x000006FC000026F4000006FC000026F4000006FC000016F4000082FC000082FC
C_CTRL_BRAM_INIT_10 0x000082F8000002FC000002FC000002FC000042E8000002FC000002FD000002FC
C_CTRL_BRAM_INIT_0F 0x000002FC000002FC0000093C000029240000093C000029240000093C00002924
C_CTRL_BRAM_INIT_0E 0x0000093C000029240000093C000029240000093C000029240000093C00002924
C_CTRL_BRAM_INIT_0D 0x0000093C000019240000803C000082FC000082F8000002FC000002FC000002FC
C_CTRL_BRAM_INIT_0C 0x000042E8000006FC000026F5000006FC000026F4000006FC000026F4000006FC
C_CTRL_BRAM_INIT_0B 0x000016F4000082FC000082FC000082F8000002FC000002FC000002FC000042E8
C_CTRL_BRAM_INIT_0A 0x000002FC000002FD000002FC000002FC000002FC0000093C000029240000093C
C_CTRL_BRAM_INIT_09 0x000029240000093C000029240000093C000019240000803C000082FC000082F8
C_CTRL_BRAM_INIT_08 0x000002FC000002FC000002FC000042E8000002FC000006FD000016F4000082FC
C_CTRL_BRAM_INIT_07 0x000082FC000082F8000002FC000002FC000002FC000042E8000002FC000002FD
C_CTRL_BRAM_INIT_06 0x000002FC000002FC000002FC0000093C000019240000803C000082FC000082F8
C_CTRL_BRAM_INIT_05 0x000002FC000002FC000002FC000042E8000002FC000002FD000016F4000082FC
C_CTRL_BRAM_INIT_04 0x000082FC000082F8000002FC000002FC000002FC000042E8000002FC000002FD
C_CTRL_BRAM_INIT_03 0x000002FC000002FC000002FC0000013C000019240000803C000082FC000082F8
C_CTRL_BRAM_INIT_02 0x000002FC000002FC000002FC000042E8000002FC000002FD000016F4000082FC
C_CTRL_BRAM_INIT_01 0x000082FC000082F8000002FC000002FC000002FC000042E8000002FC000002FD
C_CTRL_BRAM_INIT_00 0x000002FC000002FC000002FC0000013C000019240000803C000082FC000082F8
C_CTRL_BRAM_SRVAL 0x0000002FC
C_CTRL_BRAM_INITP_07 0x0000000000000000000000000000000000000000000000000000000000000000
C_CTRL_BRAM_INITP_06 0x0000000000000000000000000000000000000000000000000000000000000000
C_CTRL_BRAM_INITP_05 0x0000000000000000000000000000000000000000000000000000000000000000
C_CTRL_BRAM_INITP_04 0x0000000000000000000000000000000000000000000000000000000000000000
C_CTRL_BRAM_INITP_03 0x0000000000000000000000000000000000000000000000001111111111111111
C_CTRL_BRAM_INITP_02 0x1110000000000000000000000000000000011111111111111111111111111111
C_CTRL_BRAM_INITP_01 0x1110000000000000000011111111111111111111111111000000000111111011
C_CTRL_BRAM_INITP_00 0x1111111111110001111110111111111111111001111110111111111111111001
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


dlmb_cntlr   LMB BRAM Controller
Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus

IP Specs
Core Version Documentation
lmb_bram_if_cntlr 3.00.b IP


dlmb_cntlr IP Image
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
BRAM_PORT INITIATOR XIL_BRAM dlmb_port lmb_bram
SLMB SLAVE LMB dlmb microblaze_0


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_BASEADDR 0x00000000
C_HIGHADDR 0x0000FFFF
C_FAMILY virtex5
C_MASK 0x00800000
C_LMB_AWIDTH 32
C_LMB_DWIDTH 32
C_ECC 0
C_INTERCONNECT 0
C_FAULT_INJECT 0
C_CE_FAILING_REGISTERS 0
C_UE_FAILING_REGISTERS 0
C_ECC_STATUS_REGISTERS 0
C_ECC_ONOFF_REGISTER 0
C_ECC_ONOFF_RESET_VALUE 1
C_CE_COUNTER_WIDTH 0
C_WRITE_ACCESS 2
 
Name Value
C_SPLB_CTRL_BASEADDR 0xFFFFFFFF
C_SPLB_CTRL_HIGHADDR 0x00000000
C_SPLB_CTRL_AWIDTH 32
C_SPLB_CTRL_DWIDTH 32
C_SPLB_CTRL_P2P 0
C_SPLB_CTRL_MID_WIDTH 1
C_SPLB_CTRL_NUM_MASTERS 1
C_SPLB_CTRL_SUPPORT_BURSTS 0
C_SPLB_CTRL_NATIVE_DWIDTH 32
C_SPLB_CTRL_CLK_FREQ_HZ 100000000
C_S_AXI_CTRL_ACLK_FREQ_HZ 100000000
C_S_AXI_CTRL_BASEADDR 0xFFFFFFFF
C_S_AXI_CTRL_HIGHADDR 0x00000000
C_S_AXI_CTRL_ADDR_WIDTH 32
C_S_AXI_CTRL_DATA_WIDTH 32
C_S_AXI_CTRL_PROTOCOL AXI4LITE
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


ilmb_cntlr   LMB BRAM Controller
Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus

IP Specs
Core Version Documentation
lmb_bram_if_cntlr 3.00.b IP


ilmb_cntlr IP Image
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
BRAM_PORT INITIATOR XIL_BRAM ilmb_port lmb_bram
SLMB SLAVE LMB ilmb microblaze_0


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_BASEADDR 0x00000000
C_HIGHADDR 0x0000FFFF
C_FAMILY virtex5
C_MASK 0x00800000
C_LMB_AWIDTH 32
C_LMB_DWIDTH 32
C_ECC 0
C_INTERCONNECT 0
C_FAULT_INJECT 0
C_CE_FAILING_REGISTERS 0
C_UE_FAILING_REGISTERS 0
C_ECC_STATUS_REGISTERS 0
C_ECC_ONOFF_REGISTER 0
C_ECC_ONOFF_RESET_VALUE 1
C_CE_COUNTER_WIDTH 0
C_WRITE_ACCESS 2
 
Name Value
C_SPLB_CTRL_BASEADDR 0xFFFFFFFF
C_SPLB_CTRL_HIGHADDR 0x00000000
C_SPLB_CTRL_AWIDTH 32
C_SPLB_CTRL_DWIDTH 32
C_SPLB_CTRL_P2P 0
C_SPLB_CTRL_MID_WIDTH 1
C_SPLB_CTRL_NUM_MASTERS 1
C_SPLB_CTRL_SUPPORT_BURSTS 0
C_SPLB_CTRL_NATIVE_DWIDTH 32
C_SPLB_CTRL_CLK_FREQ_HZ 100000000
C_S_AXI_CTRL_ACLK_FREQ_HZ 100000000
C_S_AXI_CTRL_BASEADDR 0xFFFFFFFF
C_S_AXI_CTRL_HIGHADDR 0x00000000
C_S_AXI_CTRL_ADDR_WIDTH 32
C_S_AXI_CTRL_DATA_WIDTH 32
C_S_AXI_CTRL_PROTOCOL AXI4LITE
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




Peripherals TOP

DIP_Switches_8Bits   XPS General Purpose IO
General Purpose Input/Output (GPIO) core for the PLBV46 bus.

IP Specs
Core Version Documentation
xps_gpio 2.00.a IP


DIP_Switches_8Bits IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 GPIO_IO_I I 1 fpga_0_DIP_Switches_8Bits_GPIO_IO_I_pin
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
SPLB SLAVE PLBV46 mb_plb 9 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_BASEADDR 0x81420000
C_HIGHADDR 0x8142FFFF
C_SPLB_AWIDTH 32
C_SPLB_DWIDTH 32
C_SPLB_P2P 0
C_SPLB_MID_WIDTH 1
C_SPLB_NUM_MASTERS 1
C_SPLB_NATIVE_DWIDTH 32
C_SPLB_SUPPORT_BURSTS 0
C_FAMILY virtex5
 
Name Value
C_ALL_INPUTS 1
C_ALL_INPUTS_2 0
C_GPIO_WIDTH 8
C_GPIO2_WIDTH 32
C_INTERRUPT_PRESENT 0
C_DOUT_DEFAULT 0x00000000
C_TRI_DEFAULT 0xFFFFFFFF
C_IS_DUAL 0
C_DOUT_DEFAULT_2 0x00000000
C_TRI_DEFAULT_2 0xFFFFFFFF
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


ETHERNET   XPS LocalLink Tri-mode Ethernet MAC


IP Specs
Core Version Documentation
xps_ll_temac 2.03.a IP


ETHERNET IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 TemacIntc0_Irpt O 1 ETHERNET_TemacIntc0_Irpt
1 TemacPhy_RST_n O 1 fpga_0_ETHERNET_TemacPhy_RST_n_pin
2 GTX_CLK_0 I 1 clk_125_0000MHz
3 REFCLK I 1 clk_200_0000MHz
4 LlinkTemac0_CLK I 1 clk_66_6667MHzPLL0
5 MII_TX_CLK_0 I 1 mii_to_rmii_0_Rmii2Mac_tx_clk
6 MDC_0 O 1 fpga_0_ETHERNET_MDC_0_pin
7 MDIO_0 IO 1 fpga_0_ETHERNET_MDIO_0_pin
8 MII_TXD_0 O 1 ETHERNET_MII_TXD_0
9 MII_TX_ER_0 O 1 ETHERNET_MII_TX_ER_0
10 MII_TX_EN_0 O 1 ETHERNET_MII_TX_EN_0
11 MII_RXD_0 I 1 mii_to_rmii_0_Rmii2Mac_rxd
12 MII_RX_DV_0 I 1 mii_to_rmii_0_Rmii2Mac_rx_dv
13 MII_RX_ER_0 I 1 mii_to_rmii_0_Rmii2Mac_rx_er
14 MII_RX_CLK_0 I 1 mii_to_rmii_0_Rmii2Mac_rx_clk
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
LLINK0 INITIATOR XIL_LL_DMA ETHERNET_llink0 ETHERNET_fifo
SPLB SLAVE PLBV46 mb_plb 9 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_NUM_IDELAYCTRL 0
C_IDELAYCTRL_LOC NOT_SET
C_SUBFAMILY FX
C_RESERVED 0
C_SPLB_NATIVE_DWIDTH 32
C_FAMILY virtex5
C_BASEADDR 0x87000000
C_HIGHADDR 0x8707FFFF
C_SPLB_DWIDTH 32
C_SPLB_AWIDTH 32
C_SPLB_NUM_MASTERS 8
C_SPLB_MID_WIDTH 3
C_SPLB_P2P 0
C_INCLUDE_IO 0
C_PHY_TYPE 0
C_TEMAC1_ENABLED 0
C_TEMAC0_TXFIFO 16384
C_TEMAC0_RXFIFO 32768
C_TEMAC1_TXFIFO 4096
C_TEMAC1_RXFIFO 4096
C_BUS2CORE_CLK_RATIO 1
C_TEMAC_TYPE 2
C_TEMAC0_TXCSUM 0
C_TEMAC0_RXCSUM 0
 
Name Value
C_TEMAC1_TXCSUM 0
C_TEMAC1_RXCSUM 0
C_TEMAC0_PHYADDR 0B00000
C_TEMAC1_PHYADDR 0B00010
C_TEMAC0_TXVLAN_TRAN 0
C_TEMAC0_RXVLAN_TRAN 0
C_TEMAC1_TXVLAN_TRAN 0
C_TEMAC1_RXVLAN_TRAN 0
C_TEMAC0_TXVLAN_TAG 0
C_TEMAC0_RXVLAN_TAG 0
C_TEMAC1_TXVLAN_TAG 0
C_TEMAC1_RXVLAN_TAG 0
C_TEMAC0_TXVLAN_STRP 0
C_TEMAC0_RXVLAN_STRP 0
C_TEMAC1_TXVLAN_STRP 0
C_TEMAC1_RXVLAN_STRP 0
C_TEMAC0_MCAST_EXTEND 0
C_TEMAC1_MCAST_EXTEND 0
C_TEMAC0_STATS 0
C_TEMAC1_STATS 0
C_TEMAC0_AVB 0
C_TEMAC1_AVB 0
C_SIMULATION 0
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


ETHERNET_fifo   XPS LocalLink FIFO


IP Specs
Core Version Documentation
xps_ll_fifo 1.02.a IP


ETHERNET_fifo IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 IP2INTC_Irpt O 1 ETHERNET_fifo_IP2INTC_Irpt
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
SPLB SLAVE PLBV46 mb_plb 9 Peripherals.
LLINK TARGET XIL_LL_DMA ETHERNET_llink0 ETHERNET


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_SPLB_MID_WIDTH 3
C_SPLB_NUM_MASTERS 8
C_SPLB_SMALLEST_MASTER 128
C_SPLB_NATIVE_DWIDTH 32
C_SPLB_AWIDTH 32
C_BASEADDR 0x81A00000
C_HIGHADDR 0x81A0FFFF
C_SPLB_DWIDTH 32
C_SPLB_P2P 0
C_FAMILY virtex5
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


LEDs_8Bits   XPS General Purpose IO
General Purpose Input/Output (GPIO) core for the PLBV46 bus.

IP Specs
Core Version Documentation
xps_gpio 2.00.a IP


LEDs_8Bits IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 GPIO_IO_O O 1 fpga_0_LEDs_8Bits_GPIO_IO_O_pin
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
SPLB SLAVE PLBV46 mb_plb 9 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_BASEADDR 0x81400000
C_HIGHADDR 0x8140FFFF
C_SPLB_AWIDTH 32
C_SPLB_DWIDTH 32
C_SPLB_P2P 0
C_SPLB_MID_WIDTH 1
C_SPLB_NUM_MASTERS 1
C_SPLB_NATIVE_DWIDTH 32
C_SPLB_SUPPORT_BURSTS 0
C_FAMILY virtex5
 
Name Value
C_ALL_INPUTS 0
C_ALL_INPUTS_2 0
C_GPIO_WIDTH 8
C_GPIO2_WIDTH 32
C_INTERRUPT_PRESENT 0
C_DOUT_DEFAULT 0x00000000
C_TRI_DEFAULT 0xFFFFFFFF
C_IS_DUAL 0
C_DOUT_DEFAULT_2 0x00000000
C_TRI_DEFAULT_2 0xFFFFFFFF
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


RS232_Uart_1   XPS UART (Lite)
Generic UART (Universal Asynchronous Receiver/Transmitter) for PLBV46 bus.

IP Specs
Core Version Documentation
xps_uartlite 1.02.a IP


RS232_Uart_1 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 RX I 1 fpga_0_RS232_Uart_1_RX_pin
1 TX O 1 fpga_0_RS232_Uart_1_TX_pin
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
SPLB SLAVE PLBV46 mb_plb 9 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex5
C_SPLB_CLK_FREQ_HZ 100000000
C_BASEADDR 0x84000000
C_HIGHADDR 0x8400FFFF
C_SPLB_AWIDTH 32
C_SPLB_DWIDTH 32
C_SPLB_P2P 0
C_SPLB_MID_WIDTH 1
 
Name Value
C_SPLB_NUM_MASTERS 1
C_SPLB_SUPPORT_BURSTS 0
C_SPLB_NATIVE_DWIDTH 32
C_BAUDRATE 115200
C_DATA_BITS 8
C_USE_PARITY 0
C_ODD_PARITY 0
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


xps_timer_0   XPS Timer/Counter
Timer counter with PLBV46 interface

IP Specs
Core Version Documentation
xps_timer 1.02.a IP


xps_timer_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 Interrupt O 1 xps_timer_0_Interrupt
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
SPLB SLAVE PLBV46 mb_plb 9 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex5
C_COUNT_WIDTH 32
C_ONE_TIMER_ONLY 0
C_TRIG0_ASSERT 1
C_TRIG1_ASSERT 1
C_GEN0_ASSERT 1
C_GEN1_ASSERT 1
C_BASEADDR 0x83C00000
 
Name Value
C_HIGHADDR 0x83C0FFFF
C_SPLB_AWIDTH 32
C_SPLB_DWIDTH 32
C_SPLB_P2P 0
C_SPLB_MID_WIDTH 3
C_SPLB_NUM_MASTERS 8
C_SPLB_SUPPORT_BURSTS 0
C_SPLB_NATIVE_DWIDTH 32
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




IP TOP

clock_generator_0   Clock Generator
Clock generator for processor system.

IP Specs
Core Version Documentation
clock_generator 4.03.a IP


clock_generator_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 CLKIN I 1 CLK_S
1 CLKOUT0 O 1 clk_600_0000MHzPLL0_nobuf
2 CLKOUT1 O 1 clk_600_0000MHz180PLL0_nobuf
3 CLKOUT2 O 1 clk_125_0000MHz
4 CLKOUT3 O 1 clk_200_0000MHz
5 CLKOUT4 O 1 clk_66_6667MHzPLL0
6 RST I 1 sys_rst_s
7 LOCKED O 1 Dcm_all_locked
8 CLKOUT5 O 1 clk_50MHz


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_DEVICE NOT_SET
C_PACKAGE NOT_SET
C_SPEEDGRADE NOT_SET
C_CLKIN_FREQ 100000000
C_CLKOUT0_FREQ 600000000
C_CLKOUT0_PHASE 0
C_CLKOUT0_GROUP PLL0
C_CLKOUT0_BUF FALSE
C_CLKOUT0_VARIABLE_PHASE FALSE
C_CLKOUT1_FREQ 600000000
C_CLKOUT1_PHASE 180
C_CLKOUT1_GROUP PLL0
C_CLKOUT1_BUF FALSE
C_CLKOUT1_VARIABLE_PHASE FALSE
C_CLKOUT2_FREQ 125000000
C_CLKOUT2_PHASE 0
C_CLKOUT2_GROUP NONE
C_CLKOUT2_BUF TRUE
C_CLKOUT2_VARIABLE_PHASE FALSE
C_CLKOUT3_FREQ 200000000
C_CLKOUT3_PHASE 0
C_CLKOUT3_GROUP NONE
C_CLKOUT3_BUF TRUE
C_CLKOUT3_VARIABLE_PHASE FALSE
C_CLKOUT4_FREQ 66666666
C_CLKOUT4_PHASE 0
C_CLKOUT4_GROUP PLL0
C_CLKOUT4_BUF TRUE
C_CLKOUT4_VARIABLE_PHASE FALSE
C_CLKOUT5_FREQ 50000000
C_CLKOUT5_PHASE 0
C_CLKOUT5_GROUP NONE
C_CLKOUT5_BUF FALSE
C_CLKOUT5_VARIABLE_PHASE FALSE
C_CLKOUT6_FREQ 0
C_CLKOUT6_PHASE 0
C_CLKOUT6_GROUP NONE
C_CLKOUT6_BUF TRUE
C_CLKOUT6_VARIABLE_PHASE FALSE
C_CLKOUT7_FREQ 0
C_CLKOUT7_PHASE 0
C_CLKOUT7_GROUP NONE
C_CLKOUT7_BUF TRUE
C_CLKOUT7_VARIABLE_PHASE FALSE
C_CLKOUT8_FREQ 0
C_CLKOUT8_PHASE 0
C_CLKOUT8_GROUP NONE
C_CLKOUT8_BUF TRUE
C_CLKOUT8_VARIABLE_PHASE FALSE
C_CLKOUT9_FREQ 0
C_CLKOUT9_PHASE 0
C_CLKOUT9_GROUP NONE
C_CLKOUT9_BUF TRUE
C_CLKOUT9_VARIABLE_PHASE FALSE
C_CLKOUT10_FREQ 0
 
Name Value
C_CLKOUT10_PHASE 0
C_CLKOUT10_GROUP NONE
C_CLKOUT10_BUF TRUE
C_CLKOUT10_VARIABLE_PHASE FALSE
C_CLKOUT11_FREQ 0
C_CLKOUT11_PHASE 0
C_CLKOUT11_GROUP NONE
C_CLKOUT11_BUF TRUE
C_CLKOUT11_VARIABLE_PHASE FALSE
C_CLKOUT12_FREQ 0
C_CLKOUT12_PHASE 0
C_CLKOUT12_GROUP NONE
C_CLKOUT12_BUF TRUE
C_CLKOUT12_VARIABLE_PHASE FALSE
C_CLKOUT13_FREQ 0
C_CLKOUT13_PHASE 0
C_CLKOUT13_GROUP NONE
C_CLKOUT13_BUF TRUE
C_CLKOUT13_VARIABLE_PHASE FALSE
C_CLKOUT14_FREQ 0
C_CLKOUT14_PHASE 0
C_CLKOUT14_GROUP NONE
C_CLKOUT14_BUF TRUE
C_CLKOUT14_VARIABLE_PHASE FALSE
C_CLKOUT15_FREQ 0
C_CLKOUT15_PHASE 0
C_CLKOUT15_GROUP NONE
C_CLKOUT15_BUF TRUE
C_CLKOUT15_VARIABLE_PHASE FALSE
C_CLKFBIN_FREQ 0
C_CLKFBIN_DESKEW NONE
C_CLKFBOUT_FREQ 0
C_CLKFBOUT_PHASE 0
C_CLKFBOUT_GROUP NONE
C_CLKFBOUT_BUF TRUE
C_PSDONE_GROUP NONE
C_EXT_RESET_HIGH 1
C_CLK_PRIMITIVE_FEEDBACK_BUF FALSE
C_CLKOUT0_DUTY_CYCLE 0.500000
C_CLKOUT1_DUTY_CYCLE 0.500000
C_CLKOUT2_DUTY_CYCLE 0.500000
C_CLKOUT3_DUTY_CYCLE 0.500000
C_CLKOUT4_DUTY_CYCLE 0.500000
C_CLKOUT5_DUTY_CYCLE 0.500000
C_CLKOUT6_DUTY_CYCLE 0.500000
C_CLKOUT7_DUTY_CYCLE 0.500000
C_CLKOUT8_DUTY_CYCLE 0.500000
C_CLKOUT9_DUTY_CYCLE 0.500000
C_CLKOUT10_DUTY_CYCLE 0.500000
C_CLKOUT11_DUTY_CYCLE 0.500000
C_CLKOUT12_DUTY_CYCLE 0.500000
C_CLKOUT13_DUTY_CYCLE 0.500000
C_CLKOUT14_DUTY_CYCLE 0.500000
C_CLKOUT15_DUTY_CYCLE 0.500000
C_CLK_GEN UPDATE
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


mii_to_rmii_0   Ethernet PHY MII to Reduced MII
Reduced Media Independent Interface between Ethernet PHYs and Xilinx Ethernet cores such as the OPB 10/100 Ethernet MAC (opb_ethernet)

IP Specs
Core Version Documentation
mii_to_rmii 1.01.a IP


mii_to_rmii_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 Rst_n I 1 fpga_0_ETHERNET_TemacPhy_RST_n_pin
1 Rmii2Mac_rx_er O 1 mii_to_rmii_0_Rmii2Mac_rx_er
2 Rmii2Mac_rx_dv O 1 mii_to_rmii_0_Rmii2Mac_rx_dv
3 Rmii2Mac_rx_clk O 1 mii_to_rmii_0_Rmii2Mac_rx_clk
4 Rmii2Mac_tx_clk O 1 mii_to_rmii_0_Rmii2Mac_tx_clk
5 Rmii2Mac_rxd O 1 mii_to_rmii_0_Rmii2Mac_rxd
6 Rmii2Phy_tx_en O 1 mii_to_rmii_0_Rmii2Phy_tx_en
7 Rmii2Phy_txd O 1 mii_to_rmii_0_Rmii2Phy_txd
8 Phy2Rmii_crs_dv I 1 mii_to_rmii_0_Phy2Rmii_crs_dv
9 Phy2Rmii_rx_er I 1 mii_to_rmii_0_Phy2Rmii_rx_er
10 Phy2Rmii_rxd I 1 mii_to_rmii_0_Phy2Rmii_rxd
11 Mac2Rmii_tx_en I 1 ETHERNET_MII_TX_EN_0
12 Mac2Rmii_txd I 1 ETHERNET_MII_TXD_0
13 Mac2Rmii_tx_er I 1 ETHERNET_MII_TX_ER_0
14 Ref_Clk I 1 mii_to_rmii_0_Ref_Clk


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FIXED_SPEED 1
C_SPEED_100 1
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


proc_sys_reset_0   Processor System Reset Module
Reset management module

IP Specs
Core Version Documentation
proc_sys_reset 3.00.a IP


proc_sys_reset_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 Slowest_sync_clk I 1 clk_66_6667MHzPLL0
1 Ext_Reset_In I 1 sys_rst_s
2 MB_Debug_Sys_Rst I 1 Debug_SYS_Rst
3 Dcm_locked I 1 Dcm_all_locked
4 MB_Reset O 1 mb_reset
5 Bus_Struct_Reset O 1 sys_bus_reset
6 Peripheral_Reset O 1 sys_periph_reset


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_SUBFAMILY lx
C_EXT_RST_WIDTH 4
C_AUX_RST_WIDTH 4
C_EXT_RESET_HIGH 1
C_AUX_RESET_HIGH 1
C_NUM_BUS_RST 1
C_NUM_PERP_RST 1
C_NUM_INTERCONNECT_ARESETN 1
C_NUM_PERP_ARESETN 1
C_FAMILY virtex5
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




Timing Information TOP


Post Synthesis Clock Limits
No clocks could be identified in the design. Run platgen to generate synthesis information.