Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:14.1 (ISE) - P.15xf Target Family: Spartan6
OS Platform: LIN64 Target Device: xc6slx45
Project ID (random number) 0b0c56f71ec04278953e8b51677f8a8e.AA8BB0DBBDDA44D1B72EA6210FDADFD1.42 Target Package: csg484
Registration ID __123456789_123456_123456789 Target Speed: -3
Date Generated 2012-09-14T17:15:23 Tool Flow ISE
 
User Environment
OS Name RedHatEnterpriseServer OS Release Red Hat Enterprise Linux Server release 5.5 (Tikanga)
CPU Name Intel(R) Xeon(R) CPU X3220 @ 2.40GHz CPU Speed 2400.083 MHz
OS Name RedHatEnterpriseServer OS Release Red Hat Enterprise Linux Server release 5.5 (Tikanga)
CPU Name Intel(R) Xeon(R) CPU X3220 @ 2.40GHz CPU Speed 2400.083 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Comparators=2
  • 12-bit comparator equal=2
Counters=10
  • 12-bit up counter=2
  • 17-bit up counter=2
  • 2-bit up counter=1
  • 4-bit down counter=1
  • 4-bit up counter=2
  • 5-bit up counter=2
FSMs=5 Multiplexers=206
  • 1-bit 2-to-1 multiplexer=18
  • 11-bit 2-to-1 multiplexer=7
  • 5-bit 2-to-1 multiplexer=64
  • 8-bit 16-to-1 multiplexer=1
  • 8-bit 2-to-1 multiplexer=100
  • 8-bit 4-to-1 multiplexer=16
RAMs=1
  • 32x1-bit single-port distributed Read Only RAM=1
Registers=629
  • Flip-Flops=629
MiscellaneousStatistics
  • AGG_BONDED_IO=8
  • AGG_IO=8
  • AGG_LOCED_IO=8
  • AGG_SLICE=103
  • NUM_BONDED_IOB=8
  • NUM_BSFULL=162
  • NUM_BSLUTONLY=145
  • NUM_BSREGONLY=7
  • NUM_BSUSED=314
  • NUM_BUFG=1
  • NUM_LOCED_IOB=8
  • NUM_LOGIC_O5ANDO6=60
  • NUM_LOGIC_O5ONLY=50
  • NUM_LOGIC_O6ONLY=193
  • NUM_LUT_RT_DRIVES_CARRY4=4
  • NUM_LUT_RT_EXO6=4
  • NUM_LUT_RT_O5=4
  • NUM_LUT_RT_O6=50
  • NUM_RAMB16BWER=2
  • NUM_SLICEL=28
  • NUM_SLICEX=75
  • NUM_SLICE_CARRY4=16
  • NUM_SLICE_CONTROLSET=20
  • NUM_SLICE_CYINIT=425
  • NUM_SLICE_F7MUX=19
  • NUM_SLICE_F8MUX=7
  • NUM_SLICE_FF=204
  • NUM_SLICE_UNUSEDCTRL=27
  • NUM_UNUSABLE_FF_BELS=60
  • Xilinx Core blk_mem_gen_v6_2, Xilinx CORE Generator 13.2=1
  • Xilinx Core blk_mem_gen_v7_1, Xilinx CORE Generator 14.1=1
NetStatistics
  • NumNets_Active=398
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BOUNCEACROSS=12
  • NumNodesOfType_Active_BOUNCEIN=60
  • NumNodesOfType_Active_BUFGOUT=1
  • NumNodesOfType_Active_BUFHINP2OUT=3
  • NumNodesOfType_Active_CLKPIN=76
  • NumNodesOfType_Active_CLKPINFEED=3
  • NumNodesOfType_Active_CNTRLPIN=58
  • NumNodesOfType_Active_DOUBLE=312
  • NumNodesOfType_Active_GENERIC=9
  • NumNodesOfType_Active_GLOBAL=37
  • NumNodesOfType_Active_INPUT=34
  • NumNodesOfType_Active_IOBIN2OUT=7
  • NumNodesOfType_Active_IOBOUTPUT=7
  • NumNodesOfType_Active_LUTINPUT=1254
  • NumNodesOfType_Active_OUTBOUND=396
  • NumNodesOfType_Active_OUTPUT=396
  • NumNodesOfType_Active_PADINPUT=6
  • NumNodesOfType_Active_PADOUTPUT=2
  • NumNodesOfType_Active_PINBOUNCE=218
  • NumNodesOfType_Active_PINFEED=1377
  • NumNodesOfType_Active_QUAD=188
  • NumNodesOfType_Active_REGINPUT=40
  • NumNodesOfType_Active_SINGLE=555
  • NumNodesOfType_Gnd_BOUNCEACROSS=1
  • NumNodesOfType_Gnd_BOUNCEIN=23
  • NumNodesOfType_Gnd_HGNDOUT=8
  • NumNodesOfType_Gnd_INPUT=209
  • NumNodesOfType_Gnd_OUTBOUND=1
  • NumNodesOfType_Gnd_OUTPUT=1
  • NumNodesOfType_Gnd_PINBOUNCE=48
  • NumNodesOfType_Gnd_PINFEED=187
  • NumNodesOfType_Gnd_SINGLE=1
  • NumNodesOfType_Vcc_HVCCOUT=42
  • NumNodesOfType_Vcc_INPUT=2
  • NumNodesOfType_Vcc_KVCCOUT=2
  • NumNodesOfType_Vcc_LUTINPUT=114
  • NumNodesOfType_Vcc_PINBOUNCE=2
  • NumNodesOfType_Vcc_PINFEED=116
  • NumNodesOfType_Vcc_REGINPUT=2
SiteStatistics
  • BUFG-BUFGMUX=1
  • IOB-IOBM=4
  • IOB-IOBS=4
  • SLICEL-SLICEM=15
  • SLICEX-SLICEL=16
  • SLICEX-SLICEM=12
SiteSummary
  • BUFG=1
  • BUFG_BUFG=1
  • CARRY4=16
  • FF_SR=40
  • HARD0=4
  • IOB=8
  • IOB_IMUX=2
  • IOB_INBUF=2
  • IOB_OUTBUF=6
  • LUT5=114
  • LUT6=307
  • PAD=8
  • RAMB16BWER=2
  • RAMB16BWER_RAMB16BWER=2
  • REG_SR=164
  • SELMUX2_1=26
  • SLICEL=28
  • SLICEX=75
 
Configuration Data
FF_SR
  • CK=[CK:40] [CK_INV:0]
  • SRINIT=[SRINIT0:34] [SRINIT1:6]
  • SYNC_ATTR=[ASYNC:28] [SYNC:12]
IOB_OUTBUF
  • DRIVEATTRBOX=[12:6]
  • SLEW=[SLOW:6]
  • SUSPEND=[3STATE:6]
RAMB16BWER
  • CLKA=[CLKA_INV:0] [CLKA:2]
  • CLKB=[CLKB_INV:0] [CLKB:2]
  • ENA=[ENA_INV:0] [ENA:2]
  • ENB=[ENB_INV:0] [ENB:2]
  • REGCEA=[REGCEA_INV:0] [REGCEA:2]
  • REGCEB=[REGCEB_INV:0] [REGCEB:2]
  • RSTA=[RSTA:2] [RSTA_INV:0]
  • RSTB=[RSTB:2] [RSTB_INV:0]
  • WEA0=[WEA0:2] [WEA0_INV:0]
  • WEA1=[WEA1:2] [WEA1_INV:0]
  • WEA2=[WEA2:2] [WEA2_INV:0]
  • WEA3=[WEA3_INV:0] [WEA3:2]
  • WEB0=[WEB0:2] [WEB0_INV:0]
  • WEB1=[WEB1:2] [WEB1_INV:0]
  • WEB2=[WEB2_INV:0] [WEB2:2]
  • WEB3=[WEB3:2] [WEB3_INV:0]
RAMB16BWER_RAMB16BWER
  • CLKA=[CLKA_INV:0] [CLKA:2]
  • CLKB=[CLKB_INV:0] [CLKB:2]
  • DATA_WIDTH_A=[9:1] [36:1]
  • DATA_WIDTH_B=[9:1] [36:1]
  • DOA_REG=[0:2]
  • DOB_REG=[0:2]
  • ENA=[ENA_INV:0] [ENA:2]
  • ENB=[ENB_INV:0] [ENB:2]
  • EN_RSTRAM_A=[FALSE:2]
  • EN_RSTRAM_B=[FALSE:2]
  • RAM_MODE=[TDP:2]
  • REGCEA=[REGCEA_INV:0] [REGCEA:2]
  • REGCEB=[REGCEB_INV:0] [REGCEB:2]
  • RSTA=[RSTA:2] [RSTA_INV:0]
  • RSTB=[RSTB:2] [RSTB_INV:0]
  • RSTTYPE=[SYNC:2]
  • RST_PRIORITY_A=[CE:2]
  • RST_PRIORITY_B=[CE:2]
  • WEA0=[WEA0:2] [WEA0_INV:0]
  • WEA1=[WEA1:2] [WEA1_INV:0]
  • WEA2=[WEA2:2] [WEA2_INV:0]
  • WEA3=[WEA3_INV:0] [WEA3:2]
  • WEB0=[WEB0:2] [WEB0_INV:0]
  • WEB1=[WEB1:2] [WEB1_INV:0]
  • WEB2=[WEB2_INV:0] [WEB2:2]
  • WEB3=[WEB3:2] [WEB3_INV:0]
  • WRITE_MODE_A=[WRITE_FIRST:1] [READ_FIRST:1]
  • WRITE_MODE_B=[WRITE_FIRST:1] [READ_FIRST:1]
REG_SR
  • CK=[CK:164] [CK_INV:0]
  • LATCH_OR_FF=[FF:164]
  • SRINIT=[SRINIT0:154] [SRINIT1:10]
  • SYNC_ATTR=[ASYNC:110] [SYNC:54]
SLICEL
  • CLK=[CLK:18] [CLK_INV:0]
SLICEX
  • CLK=[CLK:58] [CLK_INV:0]
 
Pin Data
BUFG
  • I0=1
  • O=1
BUFG_BUFG
  • I0=1
  • O=1
CARRY4
  • CIN=12
  • CO3=12
  • CYINIT=4
  • DI0=14
  • DI1=14
  • DI2=14
  • DI3=12
  • O0=16
  • O1=14
  • O2=14
  • O3=14
  • S0=16
  • S1=14
  • S2=14
  • S3=14
FF_SR
  • CE=29
  • CK=40
  • D=40
  • Q=40
  • SR=12
HARD0
  • 0=4
IOB
  • I=2
  • O=6
  • PAD=8
IOB_IMUX
  • I=2
  • OUT=2
IOB_INBUF
  • OUT=2
  • PAD=2
IOB_OUTBUF
  • IN=6
  • OUT=6
LUT5
  • A1=27
  • A2=37
  • A3=41
  • A4=45
  • A5=50
  • O5=114
LUT6
  • A1=95
  • A2=179
  • A3=217
  • A4=258
  • A5=270
  • A6=303
  • O6=307
PAD
  • PAD=8
RAMB16BWER
  • ADDRA0=2
  • ADDRA1=2
  • ADDRA10=2
  • ADDRA11=2
  • ADDRA12=2
  • ADDRA13=2
  • ADDRA2=2
  • ADDRA3=2
  • ADDRA4=2
  • ADDRA5=2
  • ADDRA6=2
  • ADDRA7=2
  • ADDRA8=2
  • ADDRA9=2
  • ADDRB0=2
  • ADDRB1=2
  • ADDRB10=2
  • ADDRB11=2
  • ADDRB12=2
  • ADDRB13=2
  • ADDRB2=2
  • ADDRB3=2
  • ADDRB4=2
  • ADDRB5=2
  • ADDRB6=2
  • ADDRB7=2
  • ADDRB8=2
  • ADDRB9=2
  • CLKA=2
  • CLKB=2
  • DIA0=2
  • DIA1=2
  • DIA10=2
  • DIA11=2
  • DIA12=2
  • DIA13=2
  • DIA14=2
  • DIA15=2
  • DIA16=2
  • DIA17=2
  • DIA18=2
  • DIA19=2
  • DIA2=2
  • DIA20=2
  • DIA21=2
  • DIA22=2
  • DIA23=2
  • DIA24=2
  • DIA25=2
  • DIA26=2
  • DIA27=2
  • DIA28=2
  • DIA29=2
  • DIA3=2
  • DIA30=2
  • DIA31=2
  • DIA4=2
  • DIA5=2
  • DIA6=2
  • DIA7=2
  • DIA8=2
  • DIA9=2
  • DIB0=2
  • DIB1=2
  • DIB10=2
  • DIB11=2
  • DIB12=2
  • DIB13=2
  • DIB14=2
  • DIB15=2
  • DIB16=2
  • DIB17=2
  • DIB18=2
  • DIB19=2
  • DIB2=2
  • DIB20=2
  • DIB21=2
  • DIB22=2
  • DIB23=2
  • DIB24=2
  • DIB25=2
  • DIB26=2
  • DIB27=2
  • DIB28=2
  • DIB29=2
  • DIB3=2
  • DIB30=2
  • DIB31=2
  • DIB4=2
  • DIB5=2
  • DIB6=2
  • DIB7=2
  • DIB8=2
  • DIB9=2
  • DIPA0=2
  • DIPA1=2
  • DIPA2=2
  • DIPA3=2
  • DIPB0=2
  • DIPB1=2
  • DIPB2=2
  • DIPB3=2
  • DOA0=2
  • DOA1=2
  • DOA16=1
  • DOA17=1
  • DOA2=1
  • DOA24=1
  • DOA25=1
  • DOA3=1
  • DOA4=1
  • DOA5=1
  • DOA6=1
  • DOA7=1
  • DOA8=1
  • DOA9=1
  • ENA=2
  • ENB=2
  • REGCEA=2
  • REGCEB=2
  • RSTA=2
  • RSTB=2
  • WEA0=2
  • WEA1=2
  • WEA2=2
  • WEA3=2
  • WEB0=2
  • WEB1=2
  • WEB2=2
  • WEB3=2
RAMB16BWER_RAMB16BWER
  • ADDRA0=2
  • ADDRA1=2
  • ADDRA10=2
  • ADDRA11=2
  • ADDRA12=2
  • ADDRA13=2
  • ADDRA2=2
  • ADDRA3=2
  • ADDRA4=2
  • ADDRA5=2
  • ADDRA6=2
  • ADDRA7=2
  • ADDRA8=2
  • ADDRA9=2
  • ADDRB0=2
  • ADDRB1=2
  • ADDRB10=2
  • ADDRB11=2
  • ADDRB12=2
  • ADDRB13=2
  • ADDRB2=2
  • ADDRB3=2
  • ADDRB4=2
  • ADDRB5=2
  • ADDRB6=2
  • ADDRB7=2
  • ADDRB8=2
  • ADDRB9=2
  • CLKA=2
  • CLKB=2
  • DIA0=2
  • DIA1=2
  • DIA10=2
  • DIA11=2
  • DIA12=2
  • DIA13=2
  • DIA14=2
  • DIA15=2
  • DIA16=2
  • DIA17=2
  • DIA18=2
  • DIA19=2
  • DIA2=2
  • DIA20=2
  • DIA21=2
  • DIA22=2
  • DIA23=2
  • DIA24=2
  • DIA25=2
  • DIA26=2
  • DIA27=2
  • DIA28=2
  • DIA29=2
  • DIA3=2
  • DIA30=2
  • DIA31=2
  • DIA4=2
  • DIA5=2
  • DIA6=2
  • DIA7=2
  • DIA8=2
  • DIA9=2
  • DIB0=2
  • DIB1=2
  • DIB10=2
  • DIB11=2
  • DIB12=2
  • DIB13=2
  • DIB14=2
  • DIB15=2
  • DIB16=2
  • DIB17=2
  • DIB18=2
  • DIB19=2
  • DIB2=2
  • DIB20=2
  • DIB21=2
  • DIB22=2
  • DIB23=2
  • DIB24=2
  • DIB25=2
  • DIB26=2
  • DIB27=2
  • DIB28=2
  • DIB29=2
  • DIB3=2
  • DIB30=2
  • DIB31=2
  • DIB4=2
  • DIB5=2
  • DIB6=2
  • DIB7=2
  • DIB8=2
  • DIB9=2
  • DIPA0=2
  • DIPA1=2
  • DIPA2=2
  • DIPA3=2
  • DIPB0=2
  • DIPB1=2
  • DIPB2=2
  • DIPB3=2
  • DOA0=2
  • DOA1=2
  • DOA16=1
  • DOA17=1
  • DOA2=1
  • DOA24=1
  • DOA25=1
  • DOA3=1
  • DOA4=1
  • DOA5=1
  • DOA6=1
  • DOA7=1
  • DOA8=1
  • DOA9=1
  • ENA=2
  • ENB=2
  • REGCEA=2
  • REGCEB=2
  • RSTA=2
  • RSTB=2
  • WEA0=2
  • WEA1=2
  • WEA2=2
  • WEA3=2
  • WEB0=2
  • WEB1=2
  • WEB2=2
  • WEB3=2
REG_SR
  • CE=90
  • CK=164
  • D=164
  • Q=164
  • SR=54
SELMUX2_1
  • 0=25
  • 1=26
  • OUT=26
  • S0=26
SLICEL
  • A=2
  • A1=10
  • A2=10
  • A3=11
  • A4=17
  • A5=19
  • A6=27
  • AMUX=11
  • AQ=8
  • AX=7
  • B=5
  • B1=9
  • B2=11
  • B3=11
  • B4=17
  • B5=19
  • B6=25
  • BMUX=9
  • BQ=13
  • BX=7
  • C1=5
  • C2=12
  • C3=12
  • C4=18
  • C5=20
  • C6=26
  • CE=13
  • CIN=12
  • CLK=18
  • CMUX=10
  • COUT=12
  • CQ=9
  • CX=12
  • D1=10
  • D2=11
  • D3=12
  • D4=18
  • D5=20
  • D6=24
  • DMUX=8
  • DQ=8
  • DX=2
  • SR=9
SLICEX
  • A=25
  • A1=20
  • A2=40
  • A3=49
  • A4=60
  • A5=58
  • A6=61
  • AMUX=19
  • AQ=45
  • AX=6
  • B=25
  • B1=23
  • B2=40
  • B3=48
  • B4=53
  • B5=53
  • B6=56
  • BMUX=14
  • BQ=33
  • BX=2
  • C=23
  • C1=22
  • C2=40
  • C3=46
  • C4=49
  • C5=49
  • C6=49
  • CE=24
  • CLK=58
  • CMUX=16
  • CQ=29
  • CX=3
  • D=19
  • D1=13
  • D2=27
  • D3=33
  • D4=35
  • D5=35
  • D6=35
  • DMUX=9
  • DQ=19
  • DX=3
  • SR=12
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <fname>.ucf -p xc6slx45-csg484-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx45-csg484-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <fname>.ucf -p xc6slx45-csg484-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx45-csg484-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <fname>.ucf -p xc6slx45-csg484-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx45-csg484-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
bitgen 43 43 0 0 0 0 0
bitinit 1 1 0 0 0 0 0
elfcheck 1 1 0 0 0 0 0
libgen 6 2 0 0 0 0 0
map 43 43 0 0 0 0 0
ngcbuild 10 10 0 0 0 0 0
ngdbuild 43 43 0 0 0 0 0
par 43 43 0 0 0 0 0
platgen 1 1 0 0 0 0 0
trce 43 43 0 0 0 0 0
xps 6 6 0 0 0 0 0
xst 69 69 0 0 0 0 0
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_SelectedInstanceHierarchicalPath=/PmodOLEDCtrl PROP_Simulator=ISim (VHDL/Verilog)
PROP_SynthTopFile=changed PROP_Top_Level_Module_Type=HDL
PROP_UseSmartGuide=false PROP_UserConstraintEditorPreference=Text Editor
PROP_intProjectCreationTimestamp=2011-10-10T14:34:09 PROP_intWbtProjectID=AA8BB0DBBDDA44D1B72EA6210FDADFD1
PROP_intWbtProjectIteration=42 PROP_intWorkingDirLocWRTProjDir=Same
PROP_intWorkingDirUsed=No PROP_lockPinsUcfFile=changed
PROP_selectedSimRootSourceNode_behav=work.PmodOLEDCtrl PROP_AutoTop=true
PROP_DevFamily=Spartan6 PROP_DevDevice=xc6slx45
PROP_DevFamilyPMName=spartan6 PROP_DevPackage=csg484
PROP_Synthesis_Tool=XST (VHDL/Verilog) PROP_DevSpeed=-3
PROP_PreferredLanguage=VHDL FILE_COREGEN=2
FILE_UCF=1 FILE_VHDL=5
 
Core Statistics
Core Type=blk_mem_gen_v7_1
c_addra_width=9 c_addrb_width=9 c_algorithm=0 c_axi_id_width=4
c_axi_slave_type=0 c_axi_type=1 c_byte_size=9 c_common_clk=0
c_default_data=0 c_disable_warn_bhv_coll=0 c_disable_warn_bhv_range=0 c_elaboration_dir=masked_value
c_enable_32bit_address=0 c_family=spartan6 c_has_axi_id=0 c_has_ena=0
c_has_enb=0 c_has_injecterr=0 c_has_mem_output_regs_a=0 c_has_mem_output_regs_b=0
c_has_mux_output_regs_a=0 c_has_mux_output_regs_b=0 c_has_regcea=0 c_has_regceb=0
c_has_rsta=0 c_has_rstb=0 c_has_softecc_input_regs_a=0 c_has_softecc_output_regs_b=0
c_init_file_name=fname.mif c_inita_val=0 c_initb_val=0 c_interface_type=0
c_load_init_file=1 c_mem_type=0 c_mux_pipeline_stages=0 c_prim_type=5
c_read_depth_a=512 c_read_depth_b=512 c_read_width_a=8 c_read_width_b=8
c_rst_priority_a=CE c_rst_priority_b=CE c_rst_type=SYNC c_rstram_a=0
c_rstram_b=0 c_sim_collision_check=ALL c_use_byte_wea=0 c_use_byte_web=0
c_use_default_data=0 c_use_ecc=0 c_use_softecc=0 c_wea_width=1
c_web_width=1 c_write_depth_a=512 c_write_depth_b=512 c_write_mode_a=READ_FIRST
c_write_mode_b=WRITE_FIRST c_write_width_a=8 c_write_width_b=8 c_xdevicefamily=spartan6
Core Type=blk_mem_gen_v6_2
c_addra_width=11 c_addrb_width=11 c_algorithm=1 c_axi_id_width=4
c_axi_slave_type=0 c_axi_type=1 c_byte_size=9 c_common_clk=0
c_default_data=0 c_disable_warn_bhv_coll=0 c_disable_warn_bhv_range=0 c_elaboration_dir=masked_value
c_family=spartan6 c_has_axi_id=0 c_has_ena=0 c_has_enb=0
c_has_injecterr=0 c_has_mem_output_regs_a=0 c_has_mem_output_regs_b=0 c_has_mux_output_regs_a=0
c_has_mux_output_regs_b=0 c_has_regcea=0 c_has_regceb=0 c_has_rsta=0
c_has_rstb=0 c_has_softecc_input_regs_a=0 c_has_softecc_output_regs_b=0 c_init_file_name=fname.mif
c_inita_val=0 c_initb_val=0 c_interface_type=0 c_load_init_file=1
c_mem_type=3 c_mux_pipeline_stages=0 c_prim_type=1 c_read_depth_a=2048
c_read_depth_b=2048 c_read_width_a=8 c_read_width_b=8 c_rst_priority_a=CE
c_rst_priority_b=CE c_rst_type=SYNC c_rstram_a=0 c_rstram_b=0
c_sim_collision_check=ALL c_use_byte_wea=0 c_use_byte_web=0 c_use_default_data=1
c_use_ecc=0 c_use_softecc=0 c_wea_width=1 c_web_width=1
c_write_depth_a=2048 c_write_depth_b=2048 c_write_mode_a=WRITE_FIRST c_write_mode_b=WRITE_FIRST
c_write_width_a=8 c_write_width_b=8 c_xdevicefamily=spartan6
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FD=53 NGDBUILD_NUM_FDE=85 NGDBUILD_NUM_FDR=32
NGDBUILD_NUM_FDRE=32 NGDBUILD_NUM_FDSE=2 NGDBUILD_NUM_GND=4 NGDBUILD_NUM_IBUF=1
NGDBUILD_NUM_INV=15 NGDBUILD_NUM_LUT1=54 NGDBUILD_NUM_LUT2=19 NGDBUILD_NUM_LUT3=59
NGDBUILD_NUM_LUT4=44 NGDBUILD_NUM_LUT5=93 NGDBUILD_NUM_LUT6=81 NGDBUILD_NUM_MUXCY=54
NGDBUILD_NUM_MUXF7=19 NGDBUILD_NUM_MUXF8=7 NGDBUILD_NUM_OBUF=6 NGDBUILD_NUM_RAMB16BWER=2
NGDBUILD_NUM_VCC=3 NGDBUILD_NUM_XORCY=58
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_FD=53 NGDBUILD_NUM_FDE=85 NGDBUILD_NUM_FDR=32
NGDBUILD_NUM_FDRE=32 NGDBUILD_NUM_FDSE=2 NGDBUILD_NUM_GND=4 NGDBUILD_NUM_IBUF=1
NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=15 NGDBUILD_NUM_LUT1=54 NGDBUILD_NUM_LUT2=19
NGDBUILD_NUM_LUT3=59 NGDBUILD_NUM_LUT4=44 NGDBUILD_NUM_LUT5=93 NGDBUILD_NUM_LUT6=81
NGDBUILD_NUM_MUXCY=54 NGDBUILD_NUM_MUXF7=19 NGDBUILD_NUM_MUXF8=7 NGDBUILD_NUM_OBUF=6
NGDBUILD_NUM_RAMB16BWER=2 NGDBUILD_NUM_TS_TIMESPEC=1 NGDBUILD_NUM_VCC=3 NGDBUILD_NUM_XORCY=58
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ofn=<design_top> -ofmt=NGC -p=xc6slx45-3-csg484
-top=<design_top> -opt_mode=Speed -opt_level=1 -power=NO
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -sd=<No customer specific name> -write_timing_constraints=NO
-cross_clock_analysis=NO -bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100
-dsp_utilization_ratio=100 -reduce_control_sets=Auto -fsm_extract=YES -fsm_encoding=Auto
-safe_implementation=No -fsm_style=LUT -ram_extract=Yes -ram_style=Auto
-rom_extract=Yes -shreg_extract=YES -rom_style=Auto -auto_bram_packing=NO
-resource_sharing=YES -async_to_sync=NO -use_dsp48=Auto -iobuf=YES
-max_fanout=100000 -bufg=16 -register_duplication=YES -register_balancing=No
-optimize_primitives=NO -use_clock_enable=Auto -use_sync_set=Auto -use_sync_reset=Auto
-iob=Auto -equivalent_register_removal=YES -slice_utilization_ratio_maxmargin=5