PmodOLEDCtrl Project Status (09/14/2012 - 17:15:25)
Project File: PmodOLED.xise Parser Errors: No Errors
Module Name: PmodOLEDCtrl Implementation State: Programming File Generated
Target Device: xc6slx45-3csg484
  • Errors:
No Errors
Product Version:ISE 14.1
  • Warnings:
164 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 204 54,576 1%  
    Number used as Flip Flops 204      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 307 27,288 1%  
    Number used as logic 303 27,288 1%  
        Number using O6 output only 193      
        Number using O5 output only 50      
        Number using O5 and O6 60      
        Number used as ROM 0      
    Number used as Memory 0 6,408 0%  
    Number used exclusively as route-thrus 4      
        Number with same-slice register load 0      
        Number with same-slice carry load 4      
        Number with other load 0      
Number of occupied Slices 103 6,822 1%  
Nummber of MUXCYs used 64 13,644 1%  
Number of LUT Flip Flop pairs used 314      
    Number with an unused Flip Flop 145 314 46%  
    Number with an unused LUT 7 314 2%  
    Number of fully used LUT-FF pairs 162 314 51%  
    Number of unique control sets 20      
    Number of slice register sites lost
        to control set restrictions
60 54,576 1%  
Number of bonded IOBs 8 320 2%  
    Number of LOCed IOBs 8 8 100%  
Number of RAMB16BWERs 2 116 1%  
Number of RAMB8BWERs 0 232 0%  
Number of BUFIO2/BUFIO2_2CLKs 0 32 0%  
Number of BUFIO2FB/BUFIO2FB_2CLKs 0 32 0%  
Number of BUFG/BUFGMUXs 1 16 6%  
    Number used as BUFGs 1      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 0 8 0%  
Number of ILOGIC2/ISERDES2s 0 376 0%  
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 376 0%  
Number of OLOGIC2/OSERDES2s 0 376 0%  
Number of BSCANs 0 4 0%  
Number of BUFHs 0 256 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 58 0%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 0 4 0%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 3.90      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentFri Sep 14 17:14:08 20120164 Warnings (0 new)34 Infos (11 new)
Translation ReportCurrentFri Sep 14 17:14:16 2012000
Map ReportCurrentFri Sep 14 17:14:41 2012006 Infos (0 new)
Place and Route ReportCurrentFri Sep 14 17:14:59 2012000
Power Report     
Post-PAR Static Timing ReportCurrentFri Sep 14 17:15:08 2012003 Infos (0 new)
Bitgen ReportCurrentFri Sep 14 17:15:22 2012000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentFri Sep 14 17:15:23 2012
WebTalk Log FileCurrentFri Sep 14 17:15:24 2012

Date Generated: 09/14/2012 - 17:15:25