vga Project Status (04/13/2011 - 16:11:07)
Project File: FlyingLogo.xise Parser Errors: No Errors
Module Name: vga Implementation State: Programming File Not Generated
Target Device: xc6slx16-2csg324
  • Errors:
 
Product Version:ISE 12.4
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment:  
  • Final Timing Score:
  
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrent周三 四月 13 16:10:53 2011
WebTalk Log FileCurrent周三 四月 13 16:11:06 2011

Date Generated: 04/13/2011 - 16:11:07