Top Project Status
Project File: Anvyl_PmodDA2.xise Parser Errors:
Module Name: Top Implementation State: New
Target Device: xc6slx45-3csg484
  • Errors:
 
Product Version:ISE 13.4
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment:  
  • Final Timing Score:
  
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 11/22/2012 - 16:23:38