Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:13.2 (ISE) - O.61xd Target Family: Spartan6
OS Platform: NT Target Device: xc6slx45
Project ID (random number) 7ee2193a1e174d3e9b15c4e297bbd323.1958DF7D01CC4535B362D58B1C9A504C.5 Target Package: csg484
Registration ID __123456789_123456_123456789 Target Speed: -3
Date Generated 2012-08-09T10:37:18 Tool Flow ISE
 
User Environment
OS Name Microsoft Windows XP Professional OS Release Service Pack 3 (build 2600)
CPU Name Intel(R) Core(TM)2 Duo CPU T5750 @ 2.00GHz CPU Speed 1994 MHz
OS Name Microsoft Windows XP Professional OS Release Service Pack 3 (build 2600)
CPU Name Intel(R) Core(TM)2 Duo CPU T5750 @ 2.00GHz CPU Speed 1994 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Adders/Subtractors=6
  • 4-bit adder=6
Counters=2
  • 16-bit up counter=1
  • 3-bit up counter=1
FSMs=1 Multiplexers=57
  • 1-bit 2-to-1 multiplexer=48
  • 1-bit 7-to-1 multiplexer=4
  • 6-bit 2-to-1 multiplexer=5
RAMs=1
  • 16x7-bit single-port distributed Read Only RAM=1
Registers=25
  • Flip-Flops=25
MiscellaneousStatistics
  • AGG_BONDED_IO=20
  • AGG_IO=20
  • AGG_LOCED_IO=20
  • AGG_SLICE=33
  • NUM_BONDED_IOB=20
  • NUM_BSFULL=42
  • NUM_BSLUTONLY=48
  • NUM_BSUSED=90
  • NUM_BUFG=2
  • NUM_LOCED_IOB=20
  • NUM_LOGIC_O5ANDO6=18
  • NUM_LOGIC_O5ONLY=14
  • NUM_LOGIC_O6ONLY=57
  • NUM_LUT_RT_DRIVES_CARRY4=1
  • NUM_LUT_RT_EXO6=1
  • NUM_LUT_RT_O6=14
  • NUM_SLICEL=4
  • NUM_SLICEX=29
  • NUM_SLICE_CARRY4=4
  • NUM_SLICE_CONTROLSET=4
  • NUM_SLICE_CYINIT=123
  • NUM_SLICE_FF=46
  • NUM_SLICE_UNUSEDCTRL=19
  • NUM_UNUSABLE_FF_BELS=18
NetStatistics
  • NumNets_Active=138
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BOUNCEACROSS=2
  • NumNodesOfType_Active_BOUNCEIN=27
  • NumNodesOfType_Active_BUFGOUT=2
  • NumNodesOfType_Active_BUFHINP2OUT=4
  • NumNodesOfType_Active_CLKPIN=14
  • NumNodesOfType_Active_CLKPINFEED=8
  • NumNodesOfType_Active_CNTRLPIN=14
  • NumNodesOfType_Active_DOUBLE=116
  • NumNodesOfType_Active_GENERIC=27
  • NumNodesOfType_Active_GLOBAL=29
  • NumNodesOfType_Active_INPUT=5
  • NumNodesOfType_Active_IOBIN2OUT=21
  • NumNodesOfType_Active_IOBOUTPUT=21
  • NumNodesOfType_Active_LUTINPUT=353
  • NumNodesOfType_Active_OUTBOUND=126
  • NumNodesOfType_Active_OUTPUT=120
  • NumNodesOfType_Active_PADINPUT=14
  • NumNodesOfType_Active_PADOUTPUT=6
  • NumNodesOfType_Active_PINBOUNCE=52
  • NumNodesOfType_Active_PINFEED=397
  • NumNodesOfType_Active_QUAD=221
  • NumNodesOfType_Active_SINGLE=196
  • NumNodesOfType_Vcc_HVCCOUT=16
  • NumNodesOfType_Vcc_LUTINPUT=32
  • NumNodesOfType_Vcc_PINFEED=32
SiteStatistics
  • BUFG-BUFGMUX=2
  • IOB-IOBM=11
  • IOB-IOBS=9
  • SLICEL-SLICEM=4
  • SLICEX-SLICEL=3
  • SLICEX-SLICEM=8
SiteSummary
  • BUFG=2
  • BUFG_BUFG=2
  • CARRY4=4
  • FF_SR=6
  • HARD0=1
  • IOB=20
  • IOB_IMUX=6
  • IOB_INBUF=6
  • IOB_OUTBUF=14
  • LUT5=32
  • LUT6=90
  • PAD=20
  • REG_SR=40
  • SLICEL=4
  • SLICEX=29
 
Configuration Data
FF_SR
  • CK=[CK:6] [CK_INV:0]
  • SRINIT=[SRINIT0:6]
  • SYNC_ATTR=[ASYNC:6]
IOB_OUTBUF
  • DRIVEATTRBOX=[12:14]
  • SLEW=[SLOW:14]
  • SUSPEND=[3STATE:14]
REG_SR
  • CK=[CK:40] [CK_INV:0]
  • LATCH_OR_FF=[FF:40]
  • SRINIT=[SRINIT0:39] [SRINIT1:1]
  • SYNC_ATTR=[ASYNC:40]
SLICEX
  • CLK=[CLK:14] [CLK_INV:0]
 
Pin Data
BUFG
  • I0=2
  • O=2
BUFG_BUFG
  • I0=2
  • O=2
CARRY4
  • CIN=3
  • CO3=3
  • CYINIT=1
  • DI0=4
  • DI1=4
  • DI2=4
  • DI3=3
  • O0=4
  • O1=4
  • O2=4
  • O3=4
  • S0=4
  • S1=4
  • S2=4
  • S3=4
FF_SR
  • CE=1
  • CK=6
  • D=6
  • Q=6
  • SR=6
HARD0
  • 0=1
IOB
  • I=6
  • O=14
  • PAD=20
IOB_IMUX
  • I=6
  • OUT=6
IOB_INBUF
  • OUT=6
  • PAD=6
IOB_OUTBUF
  • IN=14
  • OUT=14
LUT5
  • A1=6
  • A2=14
  • A3=15
  • A4=14
  • A5=13
  • O5=32
LUT6
  • A1=39
  • A2=51
  • A3=56
  • A4=59
  • A5=88
  • A6=89
  • O6=90
PAD
  • PAD=20
REG_SR
  • CE=2
  • CK=40
  • D=40
  • Q=40
  • SR=39
SLICEL
  • A5=4
  • A6=4
  • AMUX=4
  • B5=4
  • B6=4
  • BMUX=4
  • C5=4
  • C6=4
  • CIN=3
  • CMUX=4
  • COUT=3
  • D5=3
  • D6=4
  • DMUX=4
SLICEX
  • A=16
  • A1=18
  • A2=22
  • A3=22
  • A4=22
  • A5=25
  • A6=25
  • AMUX=7
  • AQ=9
  • B=6
  • B1=8
  • B2=12
  • B3=12
  • B4=13
  • B5=17
  • B6=17
  • BMUX=5
  • BQ=11
  • C=4
  • C1=6
  • C2=8
  • C3=10
  • C4=11
  • C5=14
  • C6=14
  • CE=1
  • CLK=14
  • CMUX=1
  • CQ=11
  • D=8
  • D1=9
  • D2=10
  • D3=12
  • D4=13
  • D5=17
  • D6=17
  • DMUX=4
  • DQ=9
  • SR=13
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg484-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx45-csg484-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 12 12 0 0 0 0 0
bitgen 51 51 0 0 0 0 0
bitinit 14 14 0 0 0 0 0
cse_server 24 24 0 0 0 0 0
elfcheck 7 7 0 0 0 0 0
libgen 3 3 0 0 0 0 0
map 56 55 0 0 0 0 0
ngc2edif 2 2 0 0 0 0 0
ngcbuild 155 155 0 0 0 0 0
ngdbuild 60 59 0 0 0 0 0
par 55 54 0 0 0 0 0
platgen 50 33 0 0 0 0 0
psf2Edward 3 3 0 0 0 0 0
trce 54 54 0 0 0 0 0
xps 32 32 0 0 0 0 0
xst 340 337 0 0 0 0 0
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2012-08-06T14:03:50
PROP_intWbtProjectID=1958DF7D01CC4535B362D58B1C9A504C PROP_intWbtProjectIteration=5
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_AutoTop=true PROP_DevFamily=Spartan6
PROP_DevDevice=xc6slx45 PROP_DevFamilyPMName=spartan6
PROP_DevPackage=csg484 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-3 PROP_PreferredLanguage=VHDL
FILE_UCF=1 FILE_VHDL=5
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FD=1 NGDBUILD_NUM_FDC=41
NGDBUILD_NUM_FDCE=3 NGDBUILD_NUM_FDP=1 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=5
NGDBUILD_NUM_INV=2 NGDBUILD_NUM_LUT1=15 NGDBUILD_NUM_LUT2=19 NGDBUILD_NUM_LUT3=6
NGDBUILD_NUM_LUT4=20 NGDBUILD_NUM_LUT5=11 NGDBUILD_NUM_LUT6=34 NGDBUILD_NUM_MUXCY=15
NGDBUILD_NUM_OBUF=14 NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=16
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=2 NGDBUILD_NUM_FD=1 NGDBUILD_NUM_FDC=41 NGDBUILD_NUM_FDCE=3
NGDBUILD_NUM_FDP=1 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=5 NGDBUILD_NUM_IBUFG=1
NGDBUILD_NUM_INV=2 NGDBUILD_NUM_LUT1=15 NGDBUILD_NUM_LUT2=19 NGDBUILD_NUM_LUT3=6
NGDBUILD_NUM_LUT4=20 NGDBUILD_NUM_LUT5=11 NGDBUILD_NUM_LUT6=34 NGDBUILD_NUM_MUXCY=15
NGDBUILD_NUM_OBUF=14 NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=16
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ifmt=mixed -ofn=<design_top> -ofmt=NGC
-p=xc6slx45-3-csg484 -top=<design_top> -opt_mode=Speed -opt_level=1
-power=NO -iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized
-rtlview=Yes -glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO
-cross_clock_analysis=NO -bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100
-dsp_utilization_ratio=100 -reduce_control_sets=Auto -fsm_extract=YES -fsm_encoding=Auto
-safe_implementation=No -fsm_style=LUT -ram_extract=Yes -ram_style=Auto
-rom_extract=Yes -shreg_extract=YES -rom_style=Auto -auto_bram_packing=NO
-resource_sharing=YES -async_to_sync=NO -use_dsp48=Auto -iobuf=YES
-max_fanout=100000 -bufg=16 -register_duplication=YES -register_balancing=No
-optimize_primitives=NO -use_clock_enable=Auto -use_sync_set=Auto -use_sync_reset=Auto
-iob=Auto -equivalent_register_removal=YES -slice_utilization_ratio_maxmargin=5